Datasheet > DP83849IF_15

DP83849IF_15

更新时间： 2022-10-12 16:21:02

品牌	Logo	应用领域
德州仪器 - TI		局域网（LAN）标准
页数	文件大小	规格书
108页	786K
描述
DP83849IF PHYTER DUAL Industrial Temperature with Fiber Support (FX) and Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Tranceiver

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数据手册

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DP83849IF_15 数据手册

8.2.29 Single Clock MII (SCMII) Receive Timing

Data

IDLE

(J/K)

(TR)

PMD Input Pair

T2.29.4

T2.29.5

T2.29.1

T2.29.3

CRS

T2.29.2

RX_DV

RXD[1:0]

RX_ER

Parameter

T2.29.1

Description

Notes

25MHz Reference Clock

Min

Typ Max Units

X1 Clock Period

T2.29.2

RXD[3:0], RX_DV and RX_ER From X1 rising

output delay

T2.29.3

T2.29.4

T2.29.5

CRS ON delay (100Mb)

CRS OFF delay (100Mb)

100BASE-TX mode

bits

RXD[1:0] and RX_ER latency 100BASE-TX mode

(100Mb)

Note: Output delays assume a 25pF load.

Note: CRS is asserted and deasserted asynchronously relative to the reference clock.

Note: CRS ON delay is measured from the first bit of the JK symbol on the PMD Receive Pair to assertion of CRS_DV.

Note: CRS_OFF delay is measured from the first bit of the TR symbol on the PMD Receive Pair to deassertion of

CRS_DV.

Note: Receive Latency is measured from the first bit of the symbol pair on the PMD Receive Pair. Typical values are with

the Elasticity Buffer set to the default value (01).

103

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1...101 102 103104105 106 107 108

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