Datasheet > DP83864AUT

DP83864AUT

更新时间： 2024-02-13 17:33:32

品牌	Logo	应用领域
美国国家半导体 - NSC		以太网局域网（LAN）标准
页数	文件大小	规格书
4页	50K
描述
DP83864 Quad GigPHYTER 10/100/1000 Ethernet Physical Layer

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中文翻译

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数据手册

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DP83864AUT 数据手册

ADVANCED INFORMATION

September 2003

DP83864 Quad GigPHYTER^™

10/100/1000 Ethernet Physical Layer

General Description

Features

The DP83864 is an extremely efficient full featured Quad ■ IEEE compliant 10BASE-T,100BASE-TX, 1000BASE-T

Physical Layer transceiver with integrated PMD sublayers

to support 10BASE-T, 100BASE-TX and 1000BASE-T

Ethernet protocols.

■ Adaptive equalization and Baseline Wander comp.

■ IEEE 802.3u Auto-Negotiation and Parallel Detection

– Fully auto-negotiates between 1000 Mb/s, 100 Mb/s,

The DP83864 contains four integrated ultra low power

Gigabit Physical layers. It uses advanced 0.18 µm, 1.8 V

CMOS technology, fabricated at National’s South Portland,

Maine facilities.

and 10 Mb/s full duplex and half duplex devices

■ 2.5 V/3.3 V MAC interfaces:

– IEEE 802.3u MII with programmable bus ordering

– IEEE 802.3z GMII with programmable bus ordering

– Reduced GMII (RGMII) ver. 1.3

The DP83864 is designed for easy implementation of

10/100/1000 Mb/s Ethernet LANs. Each port interfaces

directly to Twisted Pair media via an external transformer.

This device interfaces directly to the MAC layer through the

IEEE 802.3u Standard Media Independent Interface (MII)

or the IEEE 802.3z Gigabit Media Independent Interface

(GMII). It also supports the reduced pin count RGMII (12

pins per port) and serial GMII (8 pins per port).

– Serial GMII (SGMII)

■ LED support (Link10, Link100, Link1000, Activity and

Duplex indicators); Direct drive LED’s thru management

■ User Programmable Interrupt

■ A 25Mhz or 125Mhz oscillator as reference clock input

The DP83864 is a fourth generation of Gigabit Physical

layer product with field proven architecture and perfor-

mance. Its robust performance ensures drop in replace-

ment of existing 10/100M equipment with 10/100/1000M

Networking infrastructure.

■ PHY level CRC checking on received packets and PHY

level CRC generation for test mode transmit packets

■ 292 BGA package

■ Power dissipation approximately 1 W / port

■ 1.8 V CMOS (core & analog); 2.5 V (analog & I/O); 3.3 V

Applications

is optional for 3.3 V I/O voltage

The DP83864 fits applications in:

■ One management port per chip

■ Supports Auto-MDIX/polarity at all speeds

■ One JTAG interface per chip

■ Switches with 10/100/1000 Mb/s capable ports

■ High speed uplink ports with redundancies (backbone)

■ Servers with Quad Ethernet ports

System Diagram

MII

GMII

RGMII

SGMII

Quad Port

DP83864

10BASE-T,

10/100/1000 Mb/s

ETHERNET

MAC

100BASE-TX,

1000BASE-T

ETHERNET

PHYSICAL LAYER

25 MHz or

125 MHz

Oscillator

Status

LED’s

Per Port

GigPHYTER^™is a trademark of National Semiconductor Corporation.

www.national.com

12 3 4

中文翻译

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与DP83864AUT相关器件

型号	品牌	获取价格	描述	数据表
DP83865	NSC	获取价格	DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer
DP83865	TI	获取价格	DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer
DP83865_04	NSC	获取价格	10/100/1000 Ethernet Physical Layer
DP83865BVH	NSC	获取价格	Gig PHYTER V 10/100/1000 Ethernet Physical Layer
DP83865DVH	NSC	获取价格	DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer
DP83865DVH/NOPB	TI	获取价格	DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer
DP83865DVH-NOPB	TI	获取价格	DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer
DP83867CR	TI	获取价格	采用小型 QFN 封装的低功耗、耐用型千兆以太网 PHY 收发器
DP83867CRRGZR	TI	获取价格	采用小型 QFN 封装的低功耗、耐用型千兆以太网 PHY 收发器 \| RGZ \| 48 \|
DP83867CRRGZT	TI	获取价格	采用小型 QFN 封装的低功耗、耐用型千兆以太网 PHY 收发器 \| RGZ \| 48 \|

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