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DP83901 PDF预览

DP83901

更新时间: 2024-02-19 06:11:10
品牌 Logo 应用领域
美国国家半导体 - NSC 网络接口控制器
页数 文件大小 规格书
62页 703K
描述
Serial Network Interface Controller

DP83901 技术参数

生命周期:Obsolete包装说明:QCCJ,
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.83最大数据传输速率:1.25 MBps
JESD-30 代码:S-PQCC-J68长度:24.13 mm
低功率模式:YES串行 I/O 数:1
端子数量:68封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER认证状态:Not Qualified
座面最大高度:4.57 mm标称供电电压:5 V
表面贴装:YES技术:CMOS
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:24.13 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LANBase Number Matches:1

DP83901 数据手册

 浏览型号DP83901的Datasheet PDF文件第2页浏览型号DP83901的Datasheet PDF文件第3页浏览型号DP83901的Datasheet PDF文件第4页浏览型号DP83901的Datasheet PDF文件第5页浏览型号DP83901的Datasheet PDF文件第6页浏览型号DP83901的Datasheet PDF文件第7页 
November 1995  
DP83901A SNIC  
Serial Network Interface Controller  
General Description  
Features  
Y
Compatible with IEEE 802.3, 10BASE5, 10BASE2,  
10BASE-T  
The DP83901A Serial Network Interface Controller (SNIC) is  
a microCMOS VLSI device designed for easy implementa-  
tion of CSMA/CD local area networks. These include Ether-  
net (10BASE5), Thin Ethernet (10BASE2) and Twisted-pair  
Ethernet (10BASE-T). The overall SNIC solution provides  
the Media Access Control (MAC) and Encode-Decode  
(ENDEC) functions in accordance with the IEEE 802.3 stan-  
dard.  
Y
Y
Y
Y
Dual 16-byte DMA channels  
16-byte internal FIFO  
Network statistics storage  
Supports physical, multicast and broadcast address  
filtering  
Y
10 Mbit/sec Manchester encoding and decoding plus  
clock recovery  
The integrated ENDEC module allows Manchester encod-  
ing and decoding via a differential transceiver and phase  
lock loop at 10 Mbit/sec. Also included is a collision detect  
translator and diagnostic loopback capability. (Continued)  
Y
Y
Y
Y
Y
Y
Y
Y
No external precision components required  
Efficient buffer management implementation  
Transmitter can be selected for half or full step mode  
Integrated squelch on receive and collision pairs  
3 levels of loopback supported  
Utilizes independent system and network clocks  
Lock Time 5 bits typical  
g
Decodes Manchester data with up to 18 ns jitter  
1.0 System Diagram  
TL/F/10469–1  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/10469  
RRD-B30M115/Printed in U. S. A.  

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