Datasheet > DP83849IF_15

DP83849IF_15

更新时间： 2022-10-12 16:21:02

品牌	Logo	应用领域
德州仪器 - TI		局域网（LAN）标准
页数	文件大小	规格书
108页	786K
描述
DP83849IF PHYTER DUAL Industrial Temperature with Fiber Support (FX) and Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Tranceiver

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DP83849IF_15 数据手册

8.2.27 RMII Receive Timing

IDLE

(J/K)

Data

(TR)

Data

PMD Input Pair

T2.27.4

T2.27.5

T2.27.1

T2.27.2

T2.27.3

T2.27.2

RX_DV

CRS_DV

T2.27.2

RXD[1:0]

RX_ER

Parameter

Description

X1 Clock Period

Notes

Min Typ Max Units

T2.27.1

T2.27.2

50 MHz Reference Clock

RXD[1:0], CRS_DV, RX_DV

and RX_ER output delay from

X1 rising

T2.27.3

T2.27.4

T2.27.5

CRS ON delay (100Mb)

CRS OFF delay (100Mb)

100BASE-TX mode

18.5

bits

RXD[1:0] and RX_ER latency 100BASE-TX mode

(100Mb)

Note: Per the RMII Specification, output delays assume a 25pF load.

Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may

toggle synchronously at the end of the packet to indicate CRS deassertion.

Note: RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of

receive data.

Note: CRS ON delay is measured from the first bit of the JK symbol on the PMD Receive Pair to initial assertion of

CRS_DV.

Note: CRS_OFF delay is measured from the first bit of the TR symbol on the PMD Receive Pair to initial deassertion of

CRS_DV.

Note: Receive Latency is measured from the first bit of the symbol pair on the PMD Receive Pair. Typical values are with

the Elasticity Buffer set to the default value (01).

101

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1...99 100 101102103 104 105...108

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