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DP83858

更新时间: 2024-01-31 04:52:13
品牌 Logo 应用领域
美国国家半导体 - NSC 控制器
页数 文件大小 规格书
37页 292K
描述
100 Mb/s TX/T4 Repeater Interface Controller (100RIC8⑩)

DP83858 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:PLASTIC, QFP-132针数:132
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.81Is Samacsys:N
地址总线宽度:边界扫描:NO
最大时钟频率:25 MHz最大数据传输速率:12.5 MBps
外部数据总线宽度:JESD-30 代码:S-PQFP-G132
长度:24.13 mm低功率模式:NO
串行 I/O 数:8端子数量:132
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:GQFP
封装形状:SQUARE封装形式:FLATPACK, GUARD RING
座面最大高度:4.45 mm最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.64 mm端子位置:QUAD
宽度:24.13 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches:1

DP83858 数据手册

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June 1998  
DP83858  
100 Mb/s TX/T4 Repeater Interface Controller (100RIC8)  
Supports Class II TX translational repeater and Class I  
General Description  
T4 repeater  
The DP83858 100 Mb/s TX/T4 Repeater Interface Control-  
ler, known as 100RIC8, is designed specifically to meet the  
needs of today's high speed Ethernet networking systems.  
The DP83858 is fully compatible with the IEEE 802.3  
repeater's clause 27. This device is targeted at low port  
count managed and unmanaged repeater applications.  
Supports 8 network connections (ports)  
Up to 31 repeater chips cascadable for larger hub appli-  
cations--may use DP83858 in conjunction with DP83850  
100RIC (12 ports per chip)  
Separate jabber and partition state machines for each  
port  
The DP83858 supports up to eight 100 Mb/s links with its  
network interface ports. The 100RIC8 can be configured to Management interface to DP83856 allows all repeater  
be used with either 100BASE-TX or 100BASE-T4 PHY  
technologies. Larger repeaters may be constructed by  
cascading DP83858s together using the built-in Inter  
Repeater bus.  
MIBs to be maintained  
Large per-port management counters - reduces man-  
agement CPU overhead  
On-chip elasticity buffer for PHY signal re-timing to the  
In conjunction with a DP83856 100 Mb/s Repeater Infor-  
mation Base device, a DP83858 based repeater becomes  
a managed entity that is compatible with IEEE 802.3u  
(clause 30), collecting and providing an easy interface to  
all the required network statistics.  
DP83858 clock source  
Serial register interface - reduces cost  
Physical layer device control/status access available via  
the serial register interface  
Detects repeater identification errors  
132 pin PQFP package  
Features  
IEEE 802.3u repeater and management compatible  
System Diagram  
DP83858  
DP83856  
100 Mb/s  
100 Mb/s  
Repeater Interface Controller  
(100RIC8)  
Repeater Information Base  
(100RIB)  
Inter Repeater Bus  
Management Bus  
(IR_COL, IR_DV)  
Statistics  
SRAM  
RX Enable [7..0]  
MII  
Management  
CPU  
DP83840A  
100 PHY  
#0  
DP83840A  
100 PHY  
#1  
DP83840A  
100 PHY  
#7  
DP83840A  
100 PHY  
#2  
Program  
Memory  
DP83223  
100BASE-X  
Transceiver  
DP83223  
100BASE-X  
Transceiver  
DP83223  
100BASE-X  
Transceiver  
DP83223  
100BASE-X  
Transceiver  
100Mb/s  
Ethernet  
Ports  
Management  
I/O Devices  
Port 0  
Port 1  
Port 2  
Port 7  
Note: The above system diagram depicts the repeater configured in 100BASE-TX mode.  
FAST® is a registered trademark of Fairchild Semiconductor Corporation.  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
100RICis a trademark of National Semiconductor Corporation.  
http:\\www.national.com  
1998 National Semiconductor Corporation  

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