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DNAQ20 PDF预览

DNAQ20

更新时间: 2024-11-19 06:33:31
品牌 Logo 应用领域
大兴电工 - KOA 光电二极管接口集成电路
页数 文件大小 规格书
2页 231K
描述
Diode Termination Array, 18-Line, PDSO20, QSOP-20

DNAQ20 技术参数

生命周期:Active零件包装代码:QSOP
包装说明:SSOP,针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.63
其他特性:OPERATES WITH -3V TO 7V SUPPLY差分输出:NO
接口集成电路类型:DIODE BUS TERMINATION ARRAYJESD-30 代码:R-PDSO-G20
长度:8.65 mm功能数量:1
信号线数量:18端子数量:20
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
认证状态:Not Qualified座面最大高度:1.75 mm
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL宽度:3.9116 mm
Base Number Matches:1

DNAQ20 数据手册

 浏览型号DNAQ20的Datasheet PDF文件第2页 
Electrical Characteristics  
Supply Voltage  
(VDD) . . . . . . . . . . . . . -.3V to +7V  
Channel Clamp  
Current. . . . . . . . . . . . . ±50mA  
Package Power  
Rating @ 70°C . . . . . . . 1W  
Operating  
Temperature . . . . . . . . . . 0°C to +70°C  
Storage Temperature. . . . -65°C to +150°C  
Forward Voltage  
(to VDD @ 50ma). . . . . 0.55V to 0.90V  
Forward Voltage  
(to GND @ 50ma). . . . . 0.55V to 0.85V  
Reverse Recovery  
Time (@ 50ma) . . . . . . . <400ps  
Channel Leakage  
(0<Vin<VDD) . . . . . . . 0.1µA to 5µA  
Input Capacitance  
(If = 1MHz,  
Vin = 2.5v) . . . . . . . . . . 5pF  
DNA SERIES  
Low parasitics, fast reverse recovery time, and a  
low forward voltage characteristic make KOA’s DNA  
Schottky diode network an excellent bus terminator  
for very high speed I/O. This network offers the  
designer a single package solution to address  
overshoot and undershoot problems, ringing, and  
bus reflections that are common to high speed I/O.  
Today these networks are commonly used to  
optimize bus performance in high end computers,  
external data storage peripherals, LAN networks,  
and many other applications where high transfer  
rates are necessary.  
ESD Protection . . . . . . . 4KV min.  
Circuit Schematic  
VSS  
20  
11  
10  
Features  
Negligible reverse recovery time  
G
Low capacitance  
Low forward voltage drop  
1
VDD  
18-channel terminator in a single package  
Resolved bus impedance mismatch  
Available Pin Configurations  
Applications  
n
= Number of Pins  
See physical configurations on page G-5  
for available pin/package configurations.  
Termination of data/control signals @ 66 MHz  
Dynamic RAM bus termination  
RISC architecture  
Bolivar Drive, P.O. Box 547, Bradford, PA 16701 USA  
814-362-5536  
Fax: 814-362-8883  
www.koaspeer.com  
G-4  

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