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DM74S280MX PDF预览

DM74S280MX

更新时间： 2024-01-26 11:56:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 运算电路逻辑集成电路光电二极管
页数 文件大小 规格书
5页 65K
描述
Parity Generator/Checker

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中文翻译

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DM74S280MX 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP14,.3Reach Compliance Code：unknown
风险等级：5.92Is Samacsys：N
JESD-30 代码：R-PDIP-T14JESD-609代码：e0
逻辑集成电路类型：PARITY GENERATOR/CHECKER端子数量：14
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP14,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
认证状态：Not Qualified子类别：Arithmetic Circuits
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：TTL温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

DM74S280MX 数据手册

 浏览型号DM74S280MX的Datasheet PDF文件第2页浏览型号DM74S280MX的Datasheet PDF文件第3页浏览型号DM74S280MX的Datasheet PDF文件第4页浏览型号DM74S280MX的Datasheet PDF文件第5页 
August 1986  
Revised May 2000  
DM74S280  
9-Bit Parity Generator/Checker  
General Description  
Features  
These universal, nine-bit parity generators/checkers utilize  
Schottky-clamped TTL high-performance circuitry, and fea-  
ture odd/even outputs to facilitate operation of either odd or  
even parity applications. The word-length capability is eas-  
ily expanded by cascading.  
■ Generates either odd or even parity for nine data lines  
■ Cascadable for N-bits  
■ Can be used to upgrade existing systems using MSI par-  
ity circuits  
■ Typical data-to-output delay—14 ns  
The DM74S280 can be used to upgrade the performance  
of most systems utilizing the DM74180 parity generator/  
checker. Although the DM74S280 is implemented without  
expander inputs, the corresponding function is provided by  
the availability of all input at pin 4, and no internal connec-  
tion at pin 3. This permits the DM74S280 to be substituted  
for the 180 in existing designs to produce an identical func-  
tion, even if DM74S280’s are mixed with existing 180’s.  
Input buffers are provided so that each input represents  
only one normal 74S load, and full fan-out to 10 normal  
Series 74S loads is available from each of the outputs at  
low logic levels. A fan-out to 20 normal Series 74S loads is  
provided at high logic levels, to facilitate connection of  
unused inputs to used inputs.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74S280M  
DM74S280N  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Number of Inputs  
(A Thru I) that are HIGH  
0, 2, 4, 6, 8  
Outputs  
∑ Even  
∑ Odd  
H
L
L
1, 3, 5, 7, 9  
H
© 2000 Fairchild Semiconductor Corporation  
DS006483  
www.fairchildsemi.com  
12345

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与DM74S280MX相关器件

型号 品牌 获取价格 描述 数据表
DM74S280N FAIRCHILD

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 		9-Bit Parity Generator/Checker
DM74S280N TI

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 		S SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, PDIP14, PLASTIC, DIP-14
DM74S280N/A+ ETC

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 		Parity Generator/Checker
DM74S280N/B+ ETC

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 		Parity Generator/Checker
DM74S283 FAIRCHILD

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 		4-Bit Binary Adder with Fast Carry
DM74S283J/A+ ETC

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 		Binary Adder
DM74S283N FAIRCHILD

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 		4-Bit Binary Adder with Fast Carry
DM74S283N/A+ ETC

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 		Binary Adder
DM74S283N/B+ ETC

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 		Binary Adder
DM74S287 NSC

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 		(256 x 4) 1024-BIT TTL PROM

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