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DM74S257CW PDF预览

DM74S257CW

更新时间: 2024-11-29 12:58:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 复用器
页数 文件大小 规格书
5页 50K
描述
Multiplexer, S Series, 4-Func, 2 Line Input, 1 Line Output, True Output, TTL, WAFER

DM74S257CW 技术参数

生命周期:Obsolete零件包装代码:WAFER
包装说明:DIE,Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.75
系列:SJESD-30 代码:X-XUUC-N16
逻辑集成电路类型:MULTIPLEXER功能数量:4
输入次数:2输出次数:1
端子数量:16输出特性:3-STATE
输出极性:TRUE封装主体材料:UNSPECIFIED
封装代码:DIE封装形状:UNSPECIFIED
封装形式:UNCASED CHIP传播延迟(tpd):16 ns
认证状态:Not Qualified最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
端子形式:NO LEAD端子位置:UPPER
Base Number Matches:1

DM74S257CW 数据手册

 浏览型号DM74S257CW的Datasheet PDF文件第2页浏览型号DM74S257CW的Datasheet PDF文件第3页浏览型号DM74S257CW的Datasheet PDF文件第4页浏览型号DM74S257CW的Datasheet PDF文件第5页 
August 1986  
Revised May 2000  
DM74S257  
3-STATE Quad 1-of-2 Data Selector/Multiplexer  
General Description  
Features  
These Schottky-clamped high-performance multiplexers  
feature 3-STATE outputs that can interface directly with  
data lines of bus-organized systems. With all but one of the  
common outputs disabled (at a high impedance state), the  
low impedance of the single enabled output will drive the  
bus line to a HIGH or LOW logic level. To minimize the pos-  
sibility that two outputs will attempt to take a common bus  
to opposite logic levels, the output enable circuitry is  
designed such that the output disable times are shorter  
than the output enable times.  
3-STATE versions S157, S158, with same pin-outs  
Schottky-clamped for significant improvement in  
A-C performance  
Provides bus interface from multiple sources in high-per-  
formance systems  
Average propagation delay from data input 4.8 ns  
Typical power dissipation  
320 mW  
This 3-STATE output feature means that n-bit (paralleled)  
data selectors with up to 258 sources can be implemented  
for data buses. It also permits the use of standard TTL reg-  
isters for data retention throughout the system.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74S257N  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Connection Diagram  
Function Table  
Inputs  
Select  
Output  
Output  
A
B
Y
Control  
H
L
L
L
L
X
L
X
L
X
X
X
L
Z
L
L
H
X
X
H
L
H
H
H
H
H = HIGH Level  
L = LOW Level  
X = Don’t Care  
Z = High Impedance (OFF)  
© 2000 Fairchild Semiconductor Corporation  
DS006482  
www.fairchildsemi.com  

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