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DM74LS540WM PDF预览

DM74LS540WM

更新时间: 2024-11-28 15:46:23
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
4页 97K
描述
IC LS SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, PLASTIC, SOP-20, Bus Driver/Transceiver

DM74LS540WM 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP20,.4Reach Compliance Code:unknown
风险等级:5.49其他特性:WITH DUAL OUTPUT ENABLE
控制类型:ENABLE LOW系列:LS
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):50 mA
Prop。Delay @ Nom-Sup:18 ns传播延迟(tpd):18 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

DM74LS540WM 数据手册

 浏览型号DM74LS540WM的Datasheet PDF文件第2页浏览型号DM74LS540WM的Datasheet PDF文件第3页浏览型号DM74LS540WM的Datasheet PDF文件第4页 
February 1992  
DM74LS540  
Octal Buffer/Line Driver with TRI-STATE Outputs  
É
General Description  
Features  
Y
Hysteresis at inputs to improve noise margin  
PNP inputs reduce loading  
The ‘LS540 is similar in function to the ’LS240, except that  
the inputs and outputs are on opposite sides of the package  
(see Connection Diagram). This pinout arrangement makes  
this device especially useful as an output port for microproc-  
essors, allowing ease of layout and greater PC board  
density.  
Y
Y
Y
TRI-STATE outputs drive bus lines  
Inputs and outputs opposite side of package, allowing  
easier interface to microprocessors  
Fully TTL and CMOS compatible  
Y
Connection Diagram  
Dual-In-Line Package  
TL/F/9813–1  
Order Number DM74LS540WM or DM74LS540N  
See NS Package Number M20B or N20A  
Truth Table  
Pin Name  
Description  
Inputs  
Outputs  
E1, E2  
I0–7  
Output Enable (Active Low)  
Data Inputs  
E1  
E2  
D
L
H
X
L
L
X
H
L
H
X
X
L
L
Z
Z
H
O0–7  
Data Outputs  
e
e
e
e
H
L
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
X
Z
High Impedance  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9813  
RRD-B30M115/Printed in U. S. A.  

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