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DM74LS192M PDF预览

DM74LS192M

更新时间: 2024-11-08 23:00:43
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器时钟
页数 文件大小 规格书
8页 155K
描述
54LS192/DM74LS192 Up/Down Decade Counter with Separate Up/Down Clocks

DM74LS192M 数据手册

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May 1992  
54LS192/DM74LS192 Up/Down Decade Counter  
with Separate Up/Down Clocks  
General Description  
The ’LS192 is an up/down BCD decade (8421) counter.  
Separate Count Up and Count Down Clocks are used and in  
either counting mode the circuits operate synchronously.  
The outputs change state synchronous with the LOW-to-  
HIGH transitions on the clock inputs.  
Separate Terminal Count Up and Terminal Count Down out-  
puts are provided which are used as the clocks for a subse-  
quent stage without extra logic, thus simplifying multistage  
counter designs. Individual preset inputs allow the circuits to  
be used as programmable counters. Both the Parallel Load  
(PL) and the Master Reset (MR) inputs asynchronously  
override the clocks.  
Connection Diagram  
Logic Symbol  
Dual-In-Line Package  
TL/F/10178–2  
e
V
Pin 16  
Pin 8  
CC  
e
GND  
TL/F/10178–1  
Order Number 54LS192DMQB, 54LS192FMQB,  
54LS192LMQB, DM74LS192M or DM74LS192N  
See NS Package Number E20A, J16A,  
M16A, N16E or W16A  
Mode Select Table  
Pin Names  
Description  
MR  
PL  
CP  
CP  
Mode  
U
D
CP  
CP  
Count Up Clock Input  
(Active Rising Edge)  
U
D
H
L
L
L
L
X
L
X
X
H
X
X
H
H
Reset (Asyn.)  
Preset (Asyn.)  
No Change  
Count Up  
Count Down Clock Input  
(Active Rising Edge)  
H
H
H
MR  
PL  
Asynchronous Master Reset Input  
(Active HIGH)  
L
H
L
Count Down  
Asynchronous Parallel Load Input  
(Active LOW)  
e
e
e
H
L
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
X
P0P3  
Q0Q3  
Parallel Data Inputs  
Flip-Flop Outputs  
TC  
Terminal Count Down (Borrow)  
Output (Active LOW)  
Terminal Count Up (Carry)  
Output (Active LOW)  
D
TC  
U
C
1995 National Semiconductor Corporation  
TL/F/10178  
RRD-B30M105/Printed in U. S. A.  

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