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DM74LS194AM PDF预览

DM74LS194AM

更新时间: 2024-11-08 23:00:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 71K
描述
4-Bit Bidirectional Universal Shift Register

DM74LS194AM 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.81
其他特性:HOLD MODE计数方向:BIDIRECTIONAL
系列:LSJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
逻辑集成电路类型:PARALLEL IN PARALLEL OUT最大频率@ Nom-Sup:20000000 Hz
位数:4功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):35 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Shift Registers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:20 MHzBase Number Matches:1

DM74LS194AM 数据手册

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August 1986  
Revised March 2000  
DM74LS194A  
4-Bit Bidirectional Universal Shift Register  
General Description  
Features  
This bidirectional shift register is designed to incorporate  
virtually all of the features a system designer may want in a  
shift register; they feature parallel inputs, parallel outputs,  
right-shift and left-shift serial inputs, operating-mode-con-  
trol inputs, and a direct overriding clear line. The register  
has four distinct modes of operation, namely:  
Parallel inputs and outputs  
Four operating modes:  
Synchronous parallel load  
Right shift  
Left shift  
Do nothing  
Parallel (broadside) load  
Positive edge-triggered clocking  
Direct overriding clear  
Shift right (in the direction QA toward QD)  
Shift left (in the direction QD toward QA)  
Inhibit clock (do nothing)  
Synchronous parallel loading is accomplished by applying  
the four bits of data and taking both mode control inputs,  
S0 and S1, HIGH. The data is loaded into the associated  
flip-flops and appear at the outputs after the positive transi-  
tion of the clock input. During loading, serial data flow is  
inhibited.  
Shift right is accomplished synchronously with the rising  
edge of the clock pulse when S0 is HIGH and S1 is LOW.  
Serial data for this mode is entered at the shift-right data  
input. When S0 is LOW and S1 is HIGH, data shifts left  
synchronously and new data is entered at the shift-left  
serial input.  
Clocking of the flip-flop is inhibited when both mode control  
inputs are LOW.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS194AM  
DM74LS194AN  
M16A  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
© 2000 Fairchild Semiconductor Corporation  
DS006407  
www.fairchildsemi.com  

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