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DM74LS160AMX PDF预览

DM74LS160AMX

更新时间: 2024-11-24 20:38:51
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 167K
描述
LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDSO16, 0.150 INCH, PLASTIC, SOP-16

DM74LS160AMX 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.73其他特性:TCO OUTPUT
计数方向:UP系列:LS
JESD-30 代码:R-PDSO-G16长度:9.9 mm
负载电容(CL):15 pF负载/预设输入:YES
逻辑集成电路类型:DECADE COUNTER工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE最大电源电流(ICC):31 mA
传播延迟(tpd):27 ns认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:25 MHzBase Number Matches:1

DM74LS160AMX 数据手册

 浏览型号DM74LS160AMX的Datasheet PDF文件第2页浏览型号DM74LS160AMX的Datasheet PDF文件第3页浏览型号DM74LS160AMX的Datasheet PDF文件第4页浏览型号DM74LS160AMX的Datasheet PDF文件第5页浏览型号DM74LS160AMX的Datasheet PDF文件第6页浏览型号DM74LS160AMX的Datasheet PDF文件第7页 
May 1992  
54LS160A/DM74LS160A, 54LS162A/DM74LS162A  
Synchronous Presettable BCD Decade Counters  
General Description  
Features  
Y
Synchronous counting and loading  
The ’LS160 and ’LS162 are high speed synchronous dec-  
ade counters operating in the BCD (8421) sequence. They  
are synchronously presettable for application in programma-  
ble dividers and have two types of Count Enable inputs plus  
a Terminal Count output for versatility in forming synchro-  
nous multistage counters. The ’LS160 has an asynchronous  
Master Reset input that overrides all other inputs and forces  
the outputs LOW. The ’LS162 has a Synchronous Reset  
input that overrides counting and parallel loading and allows  
all outputs to be simultaneously reset on the rising edge of  
the clock.  
Y
High speed synchronous expansion  
Y
Typical count rate of 35 MHz  
Y
Fully edge triggered  
Connection Diagram  
Dual-In-Line Package  
TL/F/10177–1  
*MR for ’LS160  
*SR for ’LS162  
Order Number 54LS160ADMQB, 54LS160AFMQB, 54LS160ALMQB,  
54LS162ADMQB, 54LS162AFMQB, 54LS162ALMQB, DM74LS160AM,  
DM74LS160AN, DM74LS162AM or DM74LS162AN  
See NS Package Number E20A, J16A, M16A, N16E or W16A  
Logic Symbol  
Pin  
Description  
Names  
CEP  
Count Enable Parallel Input  
CET  
Count Enable Trickle Input  
Clock Pulse Input (Active Rising Edge)  
Asynchronous Master Reset  
Input (Active LOW)  
CP  
MR (’160)  
SR (’162)  
Synchronous Reset  
Input (Active LOW)  
P0P3  
PE  
Parallel Data Inputs  
Parallel Enable Input  
(Active LOW)  
Q0Q3  
TC  
Flip-Flop Outputs  
TL/F/10177–2  
e
e
V
Pin 16 *MR for ’LS160  
Pin 8 *SR for ’LS162  
Terminal Count Output  
CC  
GND  
C
1995 National Semiconductor Corporation  
TL/F/10177  
RRD-B30M105/Printed in U. S. A.  

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