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DM74LS162AN PDF预览

DM74LS162AN

更新时间: 2024-11-26 23:00:43
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
9页 176K
描述
Synchronous Presettable BCD Decade Counters

DM74LS162AN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.38
其他特性:TCO OUTPUT计数方向:UP
系列:LSJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.305 mm
负载电容(CL):15 pF负载/预设输入:YES
逻辑集成电路类型:DECADE COUNTER最大频率@ Nom-Sup:25000000 Hz
最大I(ol):0.008 A工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):31 mA传播延迟(tpd):27 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Counters最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:25 MHzBase Number Matches:1

DM74LS162AN 数据手册

 浏览型号DM74LS162AN的Datasheet PDF文件第2页浏览型号DM74LS162AN的Datasheet PDF文件第3页浏览型号DM74LS162AN的Datasheet PDF文件第4页浏览型号DM74LS162AN的Datasheet PDF文件第5页浏览型号DM74LS162AN的Datasheet PDF文件第6页浏览型号DM74LS162AN的Datasheet PDF文件第7页 
May 1992  
54LS160A/DM74LS160A, 54LS162A/DM74LS162A  
Synchronous Presettable BCD Decade Counters  
General Description  
Features  
Y
Synchronous counting and loading  
The ’LS160 and ’LS162 are high speed synchronous dec-  
ade counters operating in the BCD (8421) sequence. They  
are synchronously presettable for application in programma-  
ble dividers and have two types of Count Enable inputs plus  
a Terminal Count output for versatility in forming synchro-  
nous multistage counters. The ’LS160 has an asynchronous  
Master Reset input that overrides all other inputs and forces  
the outputs LOW. The ’LS162 has a Synchronous Reset  
input that overrides counting and parallel loading and allows  
all outputs to be simultaneously reset on the rising edge of  
the clock.  
Y
High speed synchronous expansion  
Y
Typical count rate of 35 MHz  
Y
Fully edge triggered  
Connection Diagram  
Dual-In-Line Package  
TL/F/10177–1  
*MR for ’LS160  
*SR for ’LS162  
Order Number 54LS160ADMQB, 54LS160AFMQB, 54LS160ALMQB,  
54LS162ADMQB, 54LS162AFMQB, 54LS162ALMQB, DM74LS160AM,  
DM74LS160AN, DM74LS162AM or DM74LS162AN  
See NS Package Number E20A, J16A, M16A, N16E or W16A  
Logic Symbol  
Pin  
Description  
Names  
CEP  
Count Enable Parallel Input  
CET  
Count Enable Trickle Input  
Clock Pulse Input (Active Rising Edge)  
Asynchronous Master Reset  
Input (Active LOW)  
CP  
MR (’160)  
SR (’162)  
Synchronous Reset  
Input (Active LOW)  
P0P3  
PE  
Parallel Data Inputs  
Parallel Enable Input  
(Active LOW)  
Q0Q3  
TC  
Flip-Flop Outputs  
TL/F/10177–2  
e
e
V
Pin 16 *MR for ’LS160  
Pin 8 *SR for ’LS162  
Terminal Count Output  
CC  
GND  
C
1995 National Semiconductor Corporation  
TL/F/10177  
RRD-B30M105/Printed in U. S. A.  

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