March 1998
DM74LS161A/DM74LS163A
Synchronous 4-Bit Binary Counters
The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous applications without addi-
tional gating. Instrumental in accomplishing this function are
two count-enable inputs and a ripple carry output.
General Description
These synchronous, presettable counters feature an internal
carry look-ahead for application in high-speed counting de-
signs. The LS161A and LS163A are 4-bit binary counters.
The carry output is decoded by means of a NOR gate, thus
preventing spikes during the normal counting mode of op-
eration. Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the outputs change
coincident with each other when so instructed by the
count-enable inputs and internal gating. This mode of opera-
tion eliminates the output counting spikes which are normally
associated with asynchronous (ripple clock) counters. A buff-
ered clock input triggers the four flip-flops on the rising
(positive-going) edge of the clock input waveform.
Both count-enable inputs (P and T) must be high to count,
and input T is fed forward to enable the ripple carry output.
The ripple carry output thus enabled will produce a high-level
output pulse with a duration approximately equal to the
high-level portion of the QA output. This high-level overflow
ripple carry pulse can be used to enable successive cas-
caded stages. High-to-low level transitions at the enable P or
T inputs may occur, regardless of the logic level of the clock.
These counters feature a fully independent clock circuit.
Changes made to control inputs (enable P or T or load) that
will modify the operating mode have no effect until clocking
occurs. The function of the counter (whether enabled, dis-
abled, loading, or counting) will be dictated solely by the con-
ditions meeting the stable set-up and hold times.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after the
next clock pulse, regardless of the levels of the enable input.
The clear function for the LS161A is asynchronous; and a
low level at the clear input sets all four of the flip-flop outputs
low, regardless of the levels of clock, load, or enable inputs.
The clear function for the LS163A is synchronous; and a low
level at the clear inputs sets all four of the flip-flop outputs
low after the next clock pulse, regardless of the levels of the
enable inputs. This synchronous clear allows the count
length to be modified easily, as decoding the maximum
count desired can be accomplished with one external NAND
gate. The gate output is connected to the clear input to syn-
chronously clear the counter to all low outputs.
Features
n Synchronously programmable
n Internal look-ahead for fast counting
n Carry output for n-bit cascading
n Synchronous counting
n Load control line
n Diode-clamped inputs
n Typical propagation time, clock to Q output 14 ns
n Typical clock frequency 32 MHz
n Typical power dissipation 93 mW
Connection Diagram
Dual-In-Line Package
DS006397-1
Order Numbers 54LS161ADMQB, 54LS161AFMQB, 54LS161ALMQB, 54LS163ADMQB, 54LS163AFMQB,
54LS163ALMQB, DM54LS161AJ, DM54LS161AW, DM54LS163AJ, DM54LS163AW, DM74LS161AM, DM74LS161AN,
DM74LS163AM or DM74LS163AN
See Package Number E20A, J16A, M16A, N16E or W16A
© 1998 Fairchild Semiconductor Corporation
DS006397
www.fairchildsemi.com
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