DM74ALS74

更新时间： 2024-11-22 22:56:51

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
7页	72K
描述
Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear

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DM74ALS74 数据手册

September 1986

Revised February 2000

DM74ALS74A

Dual D Positive-Edge-Triggered Flip-Flop

with Preset and Clear

General Description

Features

■ Switching specifications at 50 pF

The DM74ALS74A contains two independent positive

edge-triggered flip-flops. Each flip-flop has individual D,

clock, clear and preset inputs, and also complementary Q

and Q outputs.

■ Switching specifications guaranteed over full tempera-

ture and V_CCrange

■ Advanced oxide-isolated, ion-implanted Schottky TTL

process

Information at input D is transferred to the Q output on the

positive going edge of the clock pulse. Clock triggering

occurs at a voltage level of the clock pulse and is not

directly related to the transition time of the positive going

pulse. When the clock input is at either the HIGH or LOW

level, the D input signal has no effect.

■ Functionally and pin-for-pin compatible with Schottky

and LS TTL counterpart

■ Improved AC performance over LS74 at approximately

half the power

Asynchronous preset and clear inputs will set or clear Q

output respectively upon the application of low level signal.

Ordering Code:

Order Number

DM74ALS74AM

DM74ALS74ASJ

DM74ALS74AN

Package Number Package Description

M14A

M14D

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Outputs

CLR

CLK

H (Note 1) H (Note 1)

↑

Q₀

Q ₀

L = LOW State

H = HIGH State

X = Don't Care

↑ = Positive Edge Transition

= Previous Condition of Q

Note 1: This condition is nonstable; it will not persist when preset and clear

inputs return to their inactive (HIGH) level. The output levels in this condi-

tion are not guaranteed to meet the V

specification.

DS006109

www.fairchildsemi.com

12 3 4 5 6 7

中文翻译

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与DM74ALS74相关器件

型号	品牌	获取价格	描述	数据表
DM74ALS74A	FAIRCHILD	获取价格	Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
DM74ALS74AJ	NSC	获取价格	IC,FLIP-FLOP,DUAL,D TYPE,ALS-TTL,DIP,14PIN,CERAMIC
DM74ALS74AJ/A+	ETC	获取价格	Dual D-Type Flip-Flop
DM74ALS74AM	FAIRCHILD	获取价格	Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
DM74ALS74AM/A+	NSC	获取价格	IC,FLIP-FLOP,DUAL,D TYPE,ALS-TTL,SOP,14PIN,PLASTIC
DM74ALS74AM/B+	NSC	获取价格	IC,FLIP-FLOP,DUAL,D TYPE,ALS-TTL,SOP,14PIN,PLASTIC
DM74ALS74AM_NL	FAIRCHILD	获取价格	D Flip-Flop, ALS Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, TTL
DM74ALS74AMX	NSC	获取价格	ALS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 0.150
DM74ALS74AMX_NL	FAIRCHILD	获取价格	D Flip-Flop, ALS Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, TTL
DM74ALS74AN	FAIRCHILD	获取价格	Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear

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