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DM74ALS74ASJX PDF预览

DM74ALS74ASJX

更新时间: 2024-11-08 23:47:31
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 72K
描述
Dual D-Type Flip-Flop

DM74ALS74ASJX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:5.30 MM, EIAJ TYPE2, SOP-14针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.42Is Samacsys:N
系列:ALSJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:10.2 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:34000000 Hz
最大I(ol):0.008 A湿度敏感等级:1
位数:1功能数量:2
端子数量:14最高工作温度:70 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):4 mA传播延迟(tpd):18 ns
认证状态:Not Qualified座面最大高度:2.1 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:5.3 mm
最小 fmax:34 MHzBase Number Matches:1

DM74ALS74ASJX 数据手册

 浏览型号DM74ALS74ASJX的Datasheet PDF文件第2页浏览型号DM74ALS74ASJX的Datasheet PDF文件第3页浏览型号DM74ALS74ASJX的Datasheet PDF文件第4页浏览型号DM74ALS74ASJX的Datasheet PDF文件第5页浏览型号DM74ALS74ASJX的Datasheet PDF文件第6页浏览型号DM74ALS74ASJX的Datasheet PDF文件第7页 
September 1986  
Revised February 2000  
DM74ALS74A  
Dual D Positive-Edge-Triggered Flip-Flop  
with Preset and Clear  
General Description  
Features  
Switching specifications at 50 pF  
The DM74ALS74A contains two independent positive  
edge-triggered flip-flops. Each flip-flop has individual D,  
clock, clear and preset inputs, and also complementary Q  
and Q outputs.  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
Information at input D is transferred to the Q output on the  
positive going edge of the clock pulse. Clock triggering  
occurs at a voltage level of the clock pulse and is not  
directly related to the transition time of the positive going  
pulse. When the clock input is at either the HIGH or LOW  
level, the D input signal has no effect.  
Functionally and pin-for-pin compatible with Schottky  
and LS TTL counterpart  
Improved AC performance over LS74 at approximately  
half the power  
Asynchronous preset and clear inputs will set or clear Q  
output respectively upon the application of low level signal.  
Ordering Code:  
Order Number  
DM74ALS74AM  
DM74ALS74ASJ  
DM74ALS74AN  
Package Number Package Description  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Inputs  
Outputs  
PR  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
L
X
H
L
X
H (Note 1) H (Note 1)  
H
H
H
H
H
H
H
L
L
H
L
X
Q0  
Q 0  
L = LOW State  
H = HIGH State  
X = Don't Care  
↑ = Positive Edge Transition  
= Previous Condition of Q  
Q
0
Note 1: This condition is nonstable; it will not persist when preset and clear  
inputs return to their inactive (HIGH) level. The output levels in this condi-  
tion are not guaranteed to meet the V  
specification.  
OH  
© 2000 Fairchild Semiconductor Corporation  
DS006109  
www.fairchildsemi.com  

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