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DM7438MX PDF预览

DM7438MX

更新时间: 2024-11-12 23:47:23
品牌 Logo 应用领域
其他 - ETC 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 67K
描述
Quad 2-input NAND Gate

DM7438MX 数据手册

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September 1986  
Revised July 2001  
DM7438 7438  
Quad 2-Input NAND Buffers with Open-Collector Outputs  
General Description  
Pull-Up Resistor Equations  
This device contains four independent gates each of which  
performs the logic NAND function. The open-collector out-  
puts require external pull-up resistors for proper logical  
operation.  
Where:  
N1 (IOH) = total maximum output high current  
for all outputs tied to pull-up resistor  
2 (IIH) = total maximum input high current for  
N
all inputs tied to pull-up resistor  
N3 (IIL) = total maximum input low current for  
all inputs tied to pull-up resistor  
Ordering Code:  
Order Number Package Number  
Package Description  
DM7438M  
DM7438N  
7438SJ  
M14A  
N14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = AB  
Inputs  
Output  
A
L
B
L
Y
H
H
H
L
L
H
L
H
H
H
H = HIGH Logic Level  
L = LOW Logic Level  
© 2001 Fairchild Semiconductor Corporation  
DS006513  
www.fairchildsemi.com  

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