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DM74122N PDF预览

DM74122N

更新时间: 2024-11-12 20:24:35
品牌 Logo 应用领域
德州仪器 - TI 时钟输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
6页 125K
描述
TTL/H/L SERIES, MONOSTABLE MULTIVIBRATOR, PDIP14, PLASTIC, DIP-14

DM74122N 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.46
Is Samacsys:N其他特性:RETRIGGERABLE; TRIGGERABLE FROM CLEAR INPUT ALSO
系列:TTL/H/LJESD-30 代码:R-PDIP-T14
JESD-609代码:e0长度:19.18 mm
负载电容(CL):15 pF逻辑集成电路类型:MONOSTABLE MULTIVIBRATOR
数据/时钟输入次数:4功能数量:1
端子数量:14最高工作温度:70 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):28 mA
传播延迟(tpd):40 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Prescaler/Multivibrators
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

DM74122N 数据手册

 浏览型号DM74122N的Datasheet PDF文件第2页浏览型号DM74122N的Datasheet PDF文件第3页浏览型号DM74122N的Datasheet PDF文件第4页浏览型号DM74122N的Datasheet PDF文件第5页浏览型号DM74122N的Datasheet PDF文件第6页 
June 1989  
54122/DM74122  
Retriggerable Resettable Multivibrator  
General Description  
The ’122 features positive and negative DC level triggering  
by a LOW signal applied to C , which also prevents trigger-  
D
inputs, complementary outputs, an optional 10 kX internal  
timing resistor and an overriding Direct Clear (C ) input.  
D
ing. An internal connection from C to the input gate makes  
D
it possible to trigger the circuit by a positive-going signal on  
When the circuit is in the quasi-stable (delay) state, another  
trigger applied to the inputs (per Truth Table) will cause the  
delay period to start again, without disturbing the outputs.  
This process can be repeated indefinitely and thus the out-  
put pulse period (Q HIGH, Q LOW) can be made as long as  
desired. Alternatively, a delay period can be terminated  
C , as shown in the Truth Table. For timing capacitor values  
D
greater than 1000 pF, the output pulse width is defined as  
follows:  
e
a
0.7/R )  
t
w
0.32 R C (1.0  
X
X
X
Where t is in ns, R is in kX and C is in pF.  
w
X
X
Connection Diagram  
Logic Symbol  
Dual-In-Line Package  
TL/F/10212–2  
e
V
Pin 14  
CC  
GND  
e
Pin 7  
Pins 10 and 12  
TL/F/10212–1  
Order Number 54122DMQB, 54122FMQB or DM74122N  
See NS Package Number J14A, N14A or W14B  
e
NC  
Pin Names  
Description  
A , A  
1
Trigger Inputs (Active Falling Edge)  
Trigger Inputs (Active Rising Edge)  
Direct Clear Inputs (Active LOW)  
Outputs  
2
B , B  
1
2
C
D
Q, Q  
C
1995 National Semiconductor Corporation  
TL/F/10212  
RRD-B30M105/Printed in U. S. A.  

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