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DM74123N PDF预览

DM74123N

更新时间: 2024-11-11 22:54:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 预分频器多谐振动器逻辑集成电路光电二极管输入元件时钟
页数 文件大小 规格书
5页 60K
描述
Dual Retriggerable One-Shot with Clear and Complementary Outputs

DM74123N 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.34
Is Samacsys:N其他特性:RETRIGGERABLE; TRIGGERABLE FROM CLEAR INPUT ALSO
系列:TTL/H/LJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.305 mm
逻辑集成电路类型:MONOSTABLE MULTIVIBRATOR数据/时钟输入次数:2
功能数量:2端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5 V传播延迟(tpd):40 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Prescaler/Multivibrators最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

DM74123N 数据手册

 浏览型号DM74123N的Datasheet PDF文件第2页浏览型号DM74123N的Datasheet PDF文件第3页浏览型号DM74123N的Datasheet PDF文件第4页浏览型号DM74123N的Datasheet PDF文件第5页 
August 1986  
Revised March 2000  
DM74123  
Dual Retriggerable One-Shot with  
Clear and Complementary Outputs  
General Description  
Features  
DC triggered from active-HIGH transition or active-LOW  
The DM74123 is a dual retriggerable monostable multi-  
vibrator capable of generating output pulses from a few  
nano-seconds to extremely long duration up to 100% duty  
cycle. Each device has three inputs permitting the choice of  
either leading-edge or trailing edge triggering. Pin (A) is an  
active-LOW transition trigger input and pin (B) is an active-  
HIGH transition trigger input. A LOW at the clear (CLR)  
input terminates the output pulse: which also inhibits trig-  
gering. An internal connection from CLR to the input gate  
makes it possible to trigger the circuit by a positive-going  
signal on CLR as shown in the Truth Table.  
transition inputs  
Retriggerable to 100% duty cycle  
Direct reset terminates output pulse  
Compensated for VCC and temperature variations  
DTL, TTL compatible  
Input clamp diodes  
To obtain the best and trouble free operation from this  
device please read the Operating Rules as well as the  
One–Shot Application Notes carefully and observe recom-  
mendations.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74123N  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Connection Diagram  
Triggering Truth Table  
Inputs  
Response  
A
B
X
L
CLR  
L
X
No Trigger  
No Trigger  
Trigger  
X
H
H
H
L
L
X
No Trigger  
Trigger  
H
H
Trigger  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Functional Description  
The basic output pulse width is determined by selection of  
transition clear input. Retriggering to 100% duty cycle is  
possible by application of an input pulse train whose cycle  
time is shorter than the output cycle time such that a con-  
tinuous “HIGH” logic state is maintained at the “Q” output.  
an external resistor (RX) and capacitor (CX). Once trig-  
gered, the basic pulse width may be extended by retrigger-  
ing the gated active-LOW transition or active-HIGH  
transition inputs or be reduced by use of the active-LOW  
© 2000 Fairchild Semiconductor Corporation  
DS006539  
www.fairchildsemi.com  

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