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DM54LS165J-MLS PDF预览

DM54LS165J-MLS

更新时间： 2024-11-24 14:49:03
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
6页 134K
描述
LS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, CDIP16, CERAMIC, DIP-16

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DM54LS165J-MLS 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.18
计数方向：RIGHT系列：LS
JESD-30 代码：R-GDIP-T16JESD-609代码：e0
长度：19.43 mm逻辑集成电路类型：PARALLEL IN SERIAL OUT
最大频率@ Nom-Sup：30000000 Hz位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
传播延迟（tpd）：30 ns认证状态：Not Qualified
筛选级别：38535Q/M;38534H;883B座面最大高度：5.08 mm
子类别：Shift Registers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：25 MHzBase Number Matches：1

DM54LS165J-MLS 数据手册

 浏览型号DM54LS165J-MLS的Datasheet PDF文件第2页浏览型号DM54LS165J-MLS的Datasheet PDF文件第3页浏览型号DM54LS165J-MLS的Datasheet PDF文件第4页浏览型号DM54LS165J-MLS的Datasheet PDF文件第5页浏览型号DM54LS165J-MLS的Datasheet PDF文件第6页 
May 1992  
DM54LS165/DM74LS165 8-Bit Parallel  
In/Serial Output Shift Registers  
General Description  
This device is an 8-bit serial shift register which shifts data in  
Data at the parallel inputs are loaded directly into the regis-  
ter on a high-to-low transition of the shift/load input, regard-  
less of the logic levels on the clock, clock inhibit, or serial  
inputs.  
the direction of Q toward Q when clocked. Parallel-in ac-  
H
A
cess is made available by eight individual direct data inputs,  
which are enabled by a low level at the shift/load input.  
These registers also feature gated clock inputs and comple-  
mentary outputs from the eighth bit.  
Features  
Y
Clocking is accomplished through a 2-input NOR gate, per-  
mitting one input to be used as a clock-inhibit function. Hold-  
ing either of the clock inputs high inhibits clocking, and hold-  
ing either clock input low with the load input high enables  
the other clock input. The clock-inhibit input should be  
changed to the high level only while the clock input is high.  
Parallel loading is inhibited as long as the load input is high.  
Complementary outputs  
Y
Direct overriding (data) inputs  
Y
Gated clock inputs  
Y
Parallel-to-serial data conversion  
Y
Typical frequency 35 MHz  
Y
Typical power dissipation 105 mW  
Connection Diagram  
Dual-In-Line Package  
TL/F/6399–1  
Order Number DM54LS165J, DM54LS165W, DM74LS165WM or DM74LS165N  
See NS Package Number J16A, M16B, N16E or W16A  
Function Table  
Inputs  
Clock  
Internal  
Outputs  
Output  
Shift/  
Load  
Clock  
Parallel  
A...H  
Serial  
Q
H
Inhibit  
Q
A
Q
B
L
H
H
H
H
X
L
X
X
X
H
L
a...h  
X
a
b
h
L
Q
A0  
Q
Q
Q
Q
Q
H0  
Q
Gn  
Q
Gn  
Q
H0  
B0  
An  
An  
B0  
L
X
H
u
L
X
L
u
H
X
X
X
Q
A0  
e
e
e
Low Level (steady state)  
H
X
High Level (steady state), L  
Don’t Care (any input, including transitions)  
e
Transition from low-to-high level  
u
a...h  
e
The level of steady-state input at inputs A through H, respectively.  
e
The level of Q , Q , or Q , respectively, before the indicated steady-state input conditions were established.  
A B H  
Q
Q
, Q , Q  
B0  
A0  
H0  
e
, Q  
The level of Q or Q , respectively, before the most recent  
A
transition of the clock.  
u
An  
Gn  
G
C
1995 National Semiconductor Corporation  
TL/F/6399  
RRD-B30M105/Printed in U. S. A.  
123456

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 		LS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, DIP-16
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 		IC,SHIFT REGISTER,LS-TTL,FP,16PIN,CERAMIC

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