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DM54LS169AW PDF预览

DM54LS169AW

更新时间: 2024-01-12 10:16:08
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器触发器逻辑集成电路
页数 文件大小 规格书
8页 168K
描述
Synchronous 4-Bit Up/Down Binary Counter

DM54LS169AW 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:compliant风险等级:5.25
Is Samacsys:N计数方向:BIDIRECTIONAL
JESD-30 代码:R-XDIP-T16JESD-609代码:e0
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:25000000 Hz最大I(ol):0.004 A
工作模式:SYNCHRONOUS功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5 V最大电源电流(ICC):34 mA
认证状态:Not Qualified子类别:Counters
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

DM54LS169AW 数据手册

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June 1989  
54LS169/DM54LS169A/DM74LS169A  
Synchronous 4-Bit Up/Down Binary Counter  
General Description  
This synchronous presettable counter features an internal  
carry look-ahead for cascading in high-speed counting ap-  
plications. Synchronous operation is provided by having all  
flip-flops clocked simultaneously, so that the outputs all  
change at the same time when so instructed by the count-  
enable inputs and internal gating. This mode of operation  
helps eliminate the output counting spikes that are normally  
associated with asynchronous (ripple clock) counters. A  
buffered clock input triggers the four master-slave flip-flops  
on the rising edge of the clock waveform.  
counting up, and approximately equal to the low portion of  
the Q output when counting down. This low-level overflow  
A
carry pulse can be used to enable successively cascaded  
stages. Transitions at the enable P or T inputs are allowed  
regardless of the level of the clock input. All inputs are diode  
clamped to minimize transmission-line effects, thereby sim-  
plifying system design.  
This counter features  
a fully independent clock circuit.  
Changes at control inputs (enable P, enable T, load, up/  
down), which modify the operating mode, have no effect  
until clocking occurs. The function of the counter (whether  
enabled, disabled, loading, or counting) will be dictated  
solely by the conditions meeting the stable setup and hold  
times.  
This counter is fully programmable; that is, the outputs may  
each be preset either high or low. The load input circuitry  
allows loading with the carry-enable output of cascaded  
counters. As loading is synchronous, setting up a low level  
at the load input disables the counter and causes the out-  
puts to agree with the data inputs after the next clock pulse.  
Features  
Y
The carry look-ahead circuitry permits cascading counters  
for n-bit synchronous applications without additional gating.  
Both count-enable inputs (P and T) must be low to count.  
The direction of the count is determined by the level of the  
up/down input. When the input is high, the counter counts  
up; when low, it counts down. Input T is fed forward to en-  
able the carry outputs. The carry output thus enabled will  
produce a low-level output pulse with a duration approxi-  
Fully synchronous operation for counting and  
programming.  
Y
Internal look-ahead for fast counting.  
Y
Carry output for n-bit cascading.  
Y
Fully independent clock circuit  
Y
Alternate Military/Aerospace device (54LS169) is  
a National Semiconductor Sales  
available. Contact  
Office/Distributor for specifications.  
mately equal to the high portion of the Q output when  
A
Connection Diagram  
Dual-In-Line Package  
TL/F/6401–1  
Order Number 54LS169DMQB, 54LS169FMQB, 54LS169LMQB,  
DM54LS169AJ, DM54LS169AW, DM74LS169AM or DM74LS169AN  
See NS Package Number E20A, J16A, M16A, N16E or W16A  
C
1995 National Semiconductor Corporation  
TL/F/6401  
RRD-B30M105/Printed in U. S. A.  

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