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DM54LS164W PDF预览

DM54LS164W

更新时间： 2024-11-19 22:56:47
品牌 Logo 应用领域
美国国家半导体 - NSC 移位寄存器
页数 文件大小 规格书
6页 144K
描述
8-Bit Serial In/Parallel Out Shift Registers

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中文翻译

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DM54LS164W 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.81
Is Samacsys：NJESD-30 代码：R-XDFP-F14
JESD-609代码：e0最大频率@ Nom-Sup：25000000 Hz
位数：8功能数量：1
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC
封装代码：DFP封装等效代码：FL14,.3
封装形状：RECTANGULAR封装形式：FLATPACK
电源：5 V认证状态：Not Qualified
子类别：Shift Registers标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：FLAT端子节距：1.27 mm
端子位置：DUALBase Number Matches：1

DM54LS164W 数据手册

 浏览型号DM54LS164W的Datasheet PDF文件第2页浏览型号DM54LS164W的Datasheet PDF文件第3页浏览型号DM54LS164W的Datasheet PDF文件第4页浏览型号DM54LS164W的Datasheet PDF文件第5页浏览型号DM54LS164W的Datasheet PDF文件第6页 
June 1989  
54LS164/DM54LS164/DM74LS164  
8-Bit Serial In/Parallel Out Shift Registers  
General Description  
Features  
Y
Gated (enable/disable) serial inputs  
These 8-bit shift registers feature gated serial inputs and an  
asynchronous clear. A low logic level at either input inhibits  
entry of the new data, and resets the first flip-flop to the low  
level at the next clock pulse, thus providing complete con-  
trol over incoming data. A high logic level on either input  
enables the other input, which will then determine the state  
of the first flip-flop. Data at the serial inputs may be changed  
while the clock is high or low, but only information meeting  
the setup and hold time requirements will be entered. Clock-  
ing occurs on the low-to-high level transition of the clock  
input. All inputs are diode-clamped to minimize transmis-  
sion-line effects.  
Y
Fully buffered clock and serial inputs  
Y
Asynchronous clear  
Y
Typical clock frequency 36 MHz  
Y
Typical power dissipation 80 mW  
Y
Alternate Military/Aerospace device (54LS164) is avail-  
able. Contact a National Semiconductor Sales Office/  
Distributor for specifications.  
Connection Diagram  
Function Table  
Dual-In-Line Package  
Inputs  
Clock  
Outputs  
Clear  
A
B
Q
A
Q
...  
Q
H
B
L
H
H
H
H
X
L
X
X
H
L
X
X
H
X
L
L
L
...  
...  
...  
...  
...  
L
Q
Q
B0  
Q
An  
Q
An  
Q
An  
Q
H0  
Q
Gn  
Q
Gn  
Q
Gn  
A0  
H
u
u
u
L
L
X
e
e
e
H
X
High Level (steady state), L  
Low Level (steady state)  
Don’t Care (any input, including transitions)  
e
Transition from low to high level  
u
Q
e
indicated steady-state input conditions were established.  
,
Q
B0  
,
Q
H0  
The level of  
Q , Q , or Q , respectively, before the  
A B H  
A0  
e
the clock; indicates a one-bit shift.  
Q
, Q  
The level of Q or Q before the most recent  
A
transition of  
u
An  
Gn  
G
TL/F/6398–1  
Order Number 54LS164DMQB, 54LS164FMQB,  
54LS164LMQB, DM54LS164J, DM54LS164W,  
DM74LS164M or DM74LS164N  
See NS Package Number E20A,  
J14A, M14A, N14A or W14B  
Logic Diagram  
TL/F/6398–2  
C
1995 National Semiconductor Corporation  
TL/F/6398  
RRD-B30M105/Printed in U. S. A.  
123456

中文翻译

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 		IC LS SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP14, CERA
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 		Serial In Parallel Out, LS Series, 8-Bit, Right Direction, True Output, TTL, CDFP14, CERAM
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DM54LS165J/883 TI

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 		LS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, CDIP16
DM54LS165J/883B TI

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 		IC,SHIFT REGISTER,LS-TTL,DIP,16PIN,CERAMIC
DM54LS165J/883C TI

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 		IC,SHIFT REGISTER,LS-TTL,DIP,16PIN,CERAMIC
DM54LS165J-MLS TI

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 		LS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, CDIP16
DM54LS165W NSC

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 		8-Bit Parallel In/Serial Output Shift Registers
DM54LS165W/883 ROCHESTER

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 		Parallel In Serial Out, LS Series, 8-Bit, Right Direction, Complementary Output, TTL, CDFP

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