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DM54123J PDF预览

DM54123J

更新时间: 2024-11-15 19:55:27
品牌 Logo 应用领域
美国国家半导体 - NSC 时钟逻辑集成电路
页数 文件大小 规格书
6页 129K
描述
IC 54 SERIES, DUAL MONOSTABLE MULTIVIBRATOR, CDIP16, DIP-16, Prescaler/Multivibrator

DM54123J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP-16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.75
系列:54JESD-30 代码:R-GDIP-T16
JESD-609代码:e0逻辑集成电路类型:MONOSTABLE MULTIVIBRATOR
数据/时钟输入次数:2功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):40 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Prescaler/Multivibrators最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

DM54123J 数据手册

 浏览型号DM54123J的Datasheet PDF文件第2页浏览型号DM54123J的Datasheet PDF文件第3页浏览型号DM54123J的Datasheet PDF文件第4页浏览型号DM54123J的Datasheet PDF文件第5页浏览型号DM54123J的Datasheet PDF文件第6页 
March 1993  
DM54123/DM74123 Dual Retriggerable One-Shot with  
Clear and Complementary Outputs  
General Description  
Features  
Y
DC triggered from active-high transition or active-low  
transition inputs  
The ’123 is a dual retriggerable monostable multivibrator  
capable of generating output pulses from a few nano-sec-  
onds to extremely long duration up to 100% duty cycle.  
Each device has three inputs permitting the choice of either  
leading-edge or trailing edge triggering. Pin (A) is an active-  
low transition trigger input and pin (B) is an active-high tran-  
sition trigger input. A low at the clear (CLR) input terminates  
the output pulse: which also inhibits triggering. An internal  
connection from CLR to the input gate makes it possible to  
trigger the circuit by a positive-going signal on CLR as  
shown in the truth table.  
Y
Y
Y
Y
Y
Retriggerable to 100% duty cycle  
Direct reset terminates output pulse  
Compensated for V  
and temperature variations  
CC  
DTL, TTL compatible  
Input clamp diodes  
Functional Description  
The basic output pulse width is determined by selection of  
an external resistor (R ) and capacitor (C ). Once triggered,  
X
X
To obtain the best and trouble free operation from this de-  
vice please read the operating rules as well as the NSC  
oneshot application notes carefully and observe recom-  
mendations.  
the basic pulse width may be extended by retriggering the  
gated active-low transition or active-high transition inputs or  
be reduced by use of the active-low transition clear input.  
Retriggering to 100% duty cycle is possible by application of  
an input pulse train whose cycle time is shorter than the  
output cycle time such that a continuous ‘‘HIGH’’ logic state  
is maintained at the ‘‘Q’’ output.  
Connection Diagram  
Dual-In-Line Package  
Triggering Truth Table  
Inputs  
Response  
A
B
CLR  
X
X
L
L
X
H
No Trigger  
No Trigger  
Trigger  
K
K
H
H
L
L
L
L
H
X
H
No Trigger  
Trigger  
L
Trigger  
e
e
e
H
L
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
X
TL/F/6539–1  
Order Number DM54123J-MIL, DM54123W-MIL or DM74123N  
See NS Package Number J16A, N16A or W16A  
C
1995 National Semiconductor Corporation  
TL/F/6539  
RRD-B30M105/Printed in U. S. A.  

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