Datasheet > DM512K32ST-12I

DM512K32ST-12I

更新时间： 2024-01-28 12:23:58

品牌	Logo	应用领域
铁电 - RAMTRON		动态存储器内存集成电路
页数	文件大小	规格书
21页	182K
描述
Cache DRAM Module, 512KX32, 12ns, CMOS, PSMA72

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中文翻译

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技术参数
数据手册

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DM512K32ST-12I 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	SIMM, SSIM72	Reach Compliance Code：	compliant
风险等级：	5.92	最长访问时间：	12 ns
I/O 类型：	COMMON	JESD-30 代码：	R-PSMA-N72
内存密度：	16777216 bit	内存集成电路类型：	CACHE DRAM MODULE
内存宽度：	32	端子数量：	72
字数：	524288 words	字数代码：	512000
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	512KX32	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SIMM
封装等效代码：	SSIM72	封装形状：	RECTANGULAR
封装形式：	MICROELECTRONIC ASSEMBLY	电源：	5 V
认证状态：	Not Qualified	刷新周期：	1024
座面最大高度：	24.257 mm	最大待机电流：	0.004 A
子类别：	DRAMs	最大压摆率：	0.9 mA
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	1.27 mm
端子位置：	SINGLE

DM512K32ST-12I 数据手册

DM512K32ST/DM512K36ST

512Kb x 32/512Kb x 36 EDRAM SIMM

Product Specification

Enhanced

Memory Systems Inc.

Features

Architecture

The DM512K36ST

achieves 512K x 36 density by

mounting five 512K x 8

EDRAMs, packaged in 44-pin

plastic TSOP-II packages, on

■ 4KByte SRAM Cache Memory for 12ns Random Reads Within Four

Actives Pages (Multibank Cache)

■ Fast DRAM Array for 30ns Access to Any New Page

■ Write Posting Register for 12ns Random Writes and Burst Writes

Within a Page (Hit or Miss)

■ 1KByte Wide DRAM to SRAM Bus for 56.8 Gigabytes/Sec Cache Fill

■ On-chip Cache Hit/Miss Comparators Maintain Cache Coherency

on Writes

a multi-layer substrate. Four

2203 devices and one

DM2213 device provide data

and parity storage. The

DM512K32 contains four

2203 devices for data only.

The EDRAM memory

module architecture is very

■ Hidden Precharge and Refresh Cycles

■ Extended 64ms Refresh Period for Low Standby Power

■ Standard CMOS/TTL Compatible I/O Levels and +5 Volt Supply

■ Compatibility with JEDEC 512K x 32/36 DRAM SIMM Configuration

Allows Performance Upgrade in System

■ Industrial Temperature Range Option

similar to a standard 2MB

DRAM module with the

addition of an integrated

Description

The Enhanced Memory Systems 2MB EDRAM SIMM module

provides a single memory module solution for the main memory or

local memory of fast embedded control, DSP, and other high

performance systems. Due to its fast 12ns cache row register, the

EDRAM memory module supports zero-wait-state burst read

operations at up to 50MHz bus rates in a non-interleave configuration

and 100MHz bus rates with a two-way interleave configuration.

On-chip write posting and fast page mode operation supports

12ns write and burst write operations. On a cache miss, the fast

DRAM array reloads the entire 1KByte cache over a 1KByte-wide bus

in 18ns for an effective bandwidth of 56.8 Gbytes/sec. This means

very low latency and fewer wait states on a cache miss than a non-

integrated cache/DRAM solution. The JEDEC compatible 72-bit SIMM

configuration allows a single memory controller to be designed to

support either JEDEC slow DRAMs or high speed EDRAMs to provide

a simple upgrade path to higher system performance.

cache and on-chip control which allows it to operate much like a

page mode or static column DRAM.

The EDRAM’s SRAM cache is integrated into the DRAM array as

tightly coupled row registers. The 512K x 32/36 EDRAM SIMM has a

total of four independent DRAM memory banks each with its own 256

x 32/36 SRAM row register. Memory reads always occur from the

cache row register of one of these banks as specified by row address

bits A and A (bank select). When the internal comparator detects

that the row address matches the last row read from any of the four

DRAM banks (page hit), the SRAM is accessed and data is available

on the output pins in 12ns from column address input. Subsequent

reads within the page (burst reads or random reads) can continue at

12ns cycle time. When the row address does not match the last row

read from any of the four DRAM banks (page miss), the new DRAM

row is accessed and loaded into the appropriate SRAM row register

and data is available on the output pins

all within 30ns from row enable.

Subsequent reads within the page (burst

Functional Diagram

reads or random reads) can continue at

12ns cycle time.

Since reads occur from the SRAM

cache, the DRAM precharge can occur

during burst reads. This eliminates the

precharge time delay suffered by other

DRAMs and SDRAMs when accessing a

new page. The EDRAM has an independent

on-chip refresh counter and dedicated

refresh control pin to allow the DRAM array

to be refreshed concurrently with cache

read operations (hidden refresh).

/CAL

Column

0-3, P

- A

Address

Latch

Column Decoder

4 - 256 X 36 Cache Pages

(Row Registers)

4 - 9 Bit

Comparators

Sense Amps

& Column Write Select

A - A

I/O

Control

and

Data

Latches

4 - Last Row

Read Address

Latches

0-35

Memory

Array

(2Mbyte + Parity)

Row

Address

Latch

/WE

During EDRAM read accesses, data

can be accessed in either static column

1-5

- A

W/R

/RE

Row Adress

and

Refresh

Control

Refresh

Counter

0,2

The information contained herein is subject to change without notice. Enhanced reserves the

right to change or discontinue this product without notice.

Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced 38-2113-000

80921

12 3 4 5 6 7...21

中文翻译

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与DM512K32ST-12I相关器件

型号	品牌	获取价格	描述	数据表
DM512K32ST-15	CYPRESS	获取价格	Cache DRAM Module, 512KX32, 15ns, CMOS, PSMA72,
DM512K32ST-15I	RAMTRON	获取价格	Cache DRAM Module, 512KX32, 15ns, CMOS, PSMA72
DM512K32ST-15I	CYPRESS	获取价格	Cache DRAM Module, 512KX32, 15ns, CMOS, PSMA72,
DM512K32ST6-12	ETC	获取价格	Enhanced DRAM (EDRAM) Module
DM512K32ST6-12I	ETC	获取价格	Enhanced DRAM (EDRAM) Module
DM512K32ST6-15	ETC	获取价格	Enhanced DRAM (EDRAM) Module
DM512K32ST6-15I	ETC	获取价格	Enhanced DRAM (EDRAM) Module
DM512K36ST-12	CYPRESS	获取价格	Cache DRAM Module, 512KX36, 12ns, CMOS, PSMA72,
DM512K36ST-12I	CYPRESS	获取价格	Cache DRAM Module, 512KX36, 12ns, CMOS, PSMA72,
DM512K36ST-15	CYPRESS	获取价格	Cache DRAM Module, 512KX36, 15ns, CMOS, PSMA72,

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