Datasheet > DM512K72DT6-15N

DM512K72DT6-15N

更新时间： 2024-01-23 02:06:14

品牌	Logo	应用领域
铁电 - RAMTRON		动态存储器内存集成电路
页数	文件大小	规格书
26页	254K
描述
Cache DRAM Module, 512KX72, 35ns, MOS, DIMM-168

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技术参数
数据手册

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DM512K72DT6-15N 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	DIMM, DIMM168	Reach Compliance Code：	compliant
风险等级：	5.83	Is Samacsys：	N
最长访问时间：	15 ns	I/O 类型：	COMMON
JESD-30 代码：	R-PDMA-N168	内存密度：	37748736 bit
内存集成电路类型：	EDO DRAM MODULE	内存宽度：	72
端子数量：	168	字数：	524288 words
字数代码：	512000	最高工作温度：	70 °C
最低工作温度：		组织：	512KX72
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIMM	封装等效代码：	DIMM168
封装形状：	RECTANGULAR	封装形式：	MICROELECTRONIC ASSEMBLY
电源：	5 V	认证状态：	Not Qualified
刷新周期：	1024	座面最大高度：	38.1 mm
最大待机电流：	0.011 A	子类别：	DRAMs
最大压摆率：	1.97 mA	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

DM512K72DT6-15N 数据手册

DM512K64DT6/DM512K72DT6 Multibank EDO

EDRAM

512Kb x 64/512Kb x 72 Enhanced DRAM DIMM

Enhanced

Memory Systems Inc.

Product Specification

Features

■ 8Kbytes SRAM Cache Memory for 12ns Random Reads Within Four ■ On-chip Cache Hit/Miss Comparators Automatically Maintain Cache

Active Pages (Multibank Cache)

Coherency on Writes

■ Fast 4Mbyte DRAM Array for 30ns Access to Any New Page

■ Write Posting Registers for 12ns Random Writes and Burst Writes

Within a Page (Hit or Miss)

■ Hidden Precharge & Refresh Cycles

■ Extended 64ms Refresh Period for Low Standby Power

■ CMOS/TTL Compatible I/O and +5 Volt Power Supply

■ Output Latch Enable Allows Extended Data Output (EDO) for

Faster System Operation

■ 2Kbyte Wide DRAM to SRAM Bus for 113.6 Gigabytes/Second

Cache Fill Rate

■ A Hit Pin Outputs Status on On-chip Page Hit/Miss Comparators to

Simplify Control

Description

Architecture

The DM512K72DT6 achieves

512Kb x 72 density by mounting

The Enhanced Memory Systems 4MB enhanced DRAM

(EDRAM)DIMM module provides a single memory module solution

for the main memory or local memory of fast 64-bit embedded

computers, communications switches, and other high performance

systems. Due to its fast non-interleave architecture, the EDRAM DIMM

module supports zero-wait-state burst read or write operation to

83MHz. The EDRAM outperforms conventional SRAM plus DRAM or

synchronous DRAM memory systems by minimizing wait states on

initial reads (hit or miss) and eliminating writeback delays.

Each 4Mbyte DIMM module has 8Kbytes of SRAM cache

organized as four 256 x 72 row registers with 12ns initial access

time. On a cache miss, the fast DRAM array reloads an entire 2Kbyte

row register over a 2Kbyte-wide bus in just 18ns for an effective cache

fill rate of 113.6 Gbytes/second. During write cycles, a write posting

column address is available. EDRAM supports direct non-interleave

page writes at up to 83MHz. An on-chip hit/miss comparator

automatically maintains cache coherency during writes.

nine 512Kx8 EDRAMs, packaged

in low profile 44-pin TSOP-II

packages on one side of the multi-

layer substrate. Three high drive

series terminated buffer chips

buffer address and control lines.

Twelve surface mount capacitors

are used to decouple the power

supply bus. The DM512K64DT

contains eight 512Kx8 EDRAMs.

The parity data component is not

populated.

The EDRAM memory module architecture is very similar to two

standard 2MB DRAM SIMM modules configured in a 64-bit wide,

non-interleave configuration. The EDRAM module adds an integrated

cache and cache control logic which allow the cache to operate much

like a page mode or static column DRAM.

The EDRAM’s SRAM cache is

integrated into the DRAM array as tightly

coupled row registers. Memory reads

always occur from the 256 x 72 cache

row register associated with a 1MB

Functional Diagram

0-7

Column

Add

Latch

CAL

0-8

Column Decoder

segment of DRAM. When the on-chip

4- 256 X 72 Cache Pages

(Row Register)

comparator detects a page hit, only the

4-Bit

Comp

/QLE

SRAM is accessed and data is available

Sense Amps

& Column Write Select

in 12ns from column address (the /HIT

I/O

Control

and

Data

Latches

4- Last

Row

Read

Add

Latches

output is low to indicate a page hit).

When a page miss is detected, the entire

new DRAM row is loaded into cache and

data is available at the output within

30ns from row enable (the /HIT output

is high to indicate a page miss).

0-71

0-10

Memory

Array

(4 Mbyte + Parity)

Row

Add

Latch

/WE

Subsequent reads within a page (burst

reads or random reads) will continue at

12ns cycle time. Since reads occur from

the SRAM cache, the DRAM precharge

can occur simultaneously without

degrading performance. The on-chip

refresh counter with independent

0-9

1-12

W/R

/RE

Row Add

and

Refresh

Control

Refresh

Counter

Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced

80921

38-2123-000

The information contained herein is subject to change without notice.

Enhanced reserves the right to change or discontinue this product without notice.

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与DM512K72DT6-15N相关器件

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DM512K72DTE-12N	ETC	获取价格	Enhanced DRAM (EDRAM) Module
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DM512K72DTE-15N	ETC	获取价格	Enhanced DRAM (EDRAM) Module
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DM53740-1	ITT	获取价格	D Subminiature Connectors
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