DM512K32ST6/DM512K36ST6 Multibank EDO
512Kb x 32/512Kb x 36 EDRAM SIMM
Product Specification
Enhanced
Memory Systems Inc.
Features
Architecture
The DM512K36ST6
achieves 512K x 36 density by
■ 4KByte SRAM Cache Memory for 12ns Random Reads Within Four
Actives Pages (Multibank Cache)
■ Fast DRAM Array for 30ns Access to Any New Page
■ Write Posting Register for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
■ 1KByte Wide DRAM to SRAM Bus for 56.8 Gigabytes/Sec Cache Fill
■ On-chip Cache Hit/Miss Comparators Maintain Cache Coherency
on Writes
■ EDO Mode for 83 MHz Non-Interleave Burst Rate
■ Hidden Precharge and Refresh Cycles
mounting five 512K x 8
EDRAMs, packaged in 44-pin
plastic TSOP-II packages, on a
multi-layer substrate. Four
2203 devices and one
DM2213 device provide data
and parity storage. The
DM512K32 contains four
■ Extended 64ms Refresh Period for Low Standby Power
■ Standard CMOS/TTL Compatible I/O Levels and +5 Volt Supply
■ Compatibility with JEDEC 512K x 32/36 DRAM SIMM Configuration
Allows Performance Upgrade in System
2203 devices for data only.
The EDRAM memory
module architecture is very
similar to a standard 2MB
■ Industrial Temperature Range Option
DRAM module with the
addition of an integrated
Description
cache and on-chip control which allows it to operate much like a
page mode or static column DRAM.
The Enhanced Memory Systems 2MB EDRAM SIMM module
provides a single memory module solution for the main memory or
local memory of fast embedded control, DSP, and other high
performance systems. Due to its fast 12ns cache row register, the
EDRAM memory module supports zero-wait-state burst read
operations at up to 83MHz bus rates in a non-interleave configuration
and >100MHz bus rates with a two-way interleave configuration.
On-chip write posting and fast page mode operation supports
12ns write and burst write operations. On a cache miss, the fast
DRAM array reloads the entire 1KByte cache over a 1KByte-wide bus
in 18ns for an effective bandwidth of 56.8 Gbytes/sec. This means
very low latency and fewer wait states on a cache miss than a non-
integrated cache/DRAM solution. The JEDEC compatible 72-bit SIMM
configuration allows a single memory controller to be designed to
support either JEDEC slow DRAMs or high speed EDRAMs to provide
a simple upgrade path to higher system performance.
The EDRAM’s SRAM cache is integrated into the DRAM array as
tightly coupled row registers. The 512K x 32/36 EDRAM SIMM has a
total of four independent DRAM memory banks each with its own 256
x 32/36 SRAM row register. Memory reads always occur from the
cache row register of one of these banks as specified by row address
bits A and A (bank select). When the internal comparator detects
8
9
that the row address matches the last row read from any of the four
DRAM banks (page hit), the SRAM is accessed and data is available
on the output pins in 12ns from column address input. Subsequent
reads within the page (burst reads or random reads) can continue at
12ns cycle time. When the row address does not match the last row
read from any of the four DRAM banks (page miss), the new DRAM
row is accessed and loaded into the appropriate SRAM row register
and data is available on the output pins
all within 30ns from row enable.
Subsequent reads within the page (burst
Functional Diagram
reads or random reads) can continue at
12ns cycle time. During either read hit or
/CAL
Column
0-3, P
A
- A
7
Address
Latch
0
read miss operations, the EDO option
Column Decoder
extends data output time to allow use of
4 - 256 X 36 Cache Pages
(Row Registers)
the full 83Mbyte/second bandwidth.
4 - 9 Bit
Comparators
Since reads occur from the SRAM
Sense Amps
& Column Write Select
cache, the DRAM precharge can occur
/G
A - A
10
I/O
Control
and
Data
Latches
during burst reads. This eliminates the
0
4 - Last Row
Read Address
Latches
DQ
0-35
precharge time delay suffered by other
DRAMs and SDRAMs when accessing a
new page. The EDRAM has an
/S
Memory
Array
2Mbyte + Parity
Row
Address
Latch
/WE
independent on-chip refresh counter and
dedicated refresh control pin to allow the
DRAM array to be refreshed concurrently
with cache read operations (hidden
refresh).
V
CC
C
1-5
A
- A
V
0
9
SS
/F
W/R
/RE
Row Adress
and
Refresh
Control
Refresh
Counter
0, 2
The information contained herein is subject to change without notice. Enhanced reserves the
right to change or discontinue this product without notice.
© 1996 Enhanced Memory Sytems Inc, 1850 Ramtron Drive, Colorado Springs, CO
Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced 38-2117-000
80921