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DG202CJ

更新时间： 2024-01-04 14:31:45
品牌 Logo 应用领域
英特矽尔 - INTERSIL 开关光电二极管输出元件
页数 文件大小 规格书
7页 74K
描述
Quad SPST, CMOS Analog Switches

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DG202CJ 技术参数

生命周期：Transferred包装说明：CERAMIC, DIP
Reach Compliance Code：unknown风险等级：5.56
模拟集成电路 - 其他类型：SPSTJESD-30 代码：R-CDIP-T
信道数量：4功能数量：1
最大通态电阻 (Ron)：175 Ω封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装形状：RECTANGULAR封装形式：IN-LINE
认证状态：Not Qualified最大供电电压 (Vsup)：44 V
表面贴装：NO最长接通时间：600 ns
端子形式：THROUGH-HOLE端子位置：DUAL
Base Number Matches：1

DG202CJ 数据手册

 浏览型号DG202CJ的Datasheet PDF文件第1页浏览型号DG202CJ的Datasheet PDF文件第2页浏览型号DG202CJ的Datasheet PDF文件第3页浏览型号DG202CJ的Datasheet PDF文件第4页浏览型号DG202CJ的Datasheet PDF文件第5页浏览型号DG202CJ的Datasheet PDF文件第6页 
DG201A, DG202  
Small Outline Plastic Packages (SOIC)  
M16.3 (JEDEC MS-013-AA ISSUE C)  
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE  
INDEX  
AREA  
0.25(0.010)  
M
B M  
H
INCHES  
MILLIMETERS  
E
SYMBOL  
MIN  
MAX  
MIN  
2.35  
0.10  
0.33  
0.23  
MAX  
2.65  
0.30  
0.51  
0.32  
10.50  
7.60  
NOTES  
-B-  
A
A1  
B
C
D
E
e
0.0926  
0.0040  
0.013  
0.1043  
0.0118  
0.0200  
0.0125  
-
-
1
2
3
L
9
SEATING PLANE  
A
0.0091  
0.3977  
0.2914  
-
-A-  
o
0.4133 10.10  
3
h x 45  
D
0.2992  
7.40  
4
-C-  
0.050 BSC  
1.27 BSC  
-
α
H
h
0.394  
0.010  
0.016  
0.419  
0.029  
0.050  
10.00  
0.25  
0.40  
10.65  
0.75  
1.27  
-
e
A1  
C
5
B
0.10(0.004)  
L
6
0.25(0.010) M  
C
A M B S  
N
α
16  
16  
7
o
o
o
o
0
8
0
8
-
NOTES:  
Rev. 0 12/93  
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of  
Publication Number 95.  
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
3. Dimension “D” does not include mold flash, protrusions or gate burrs.  
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006  
inch) per side.  
4. Dimension “E” does not include interlead flash or protrusions. Interlead  
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.  
5. The chamfer on the body is optional. If it is not present, a visual index  
feature must be located within the crosshatched area.  
6. “L” is the length of terminal for soldering to a substrate.  
7. “N” is the number of terminal positions.  
8. Terminal numbers are shown for reference only.  
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above  
the seating plane, shall not exceed a maximum value of 0.61mm (0.024  
inch)  
10. Controlling dimension: MILLIMETER. Converted inch dimensions are  
not necessarily exact.  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Mercure Center  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
Intersil (Taiwan) Ltd.  
7F-6, No. 101 Fu Hsing North Road  
Taipei, Taiwan  
Republic of China  
TEL: (886) 2 2716 9310  
FAX: (886) 2 2715 3029  
P. O. Box 883, Mail Stop 53-204  
Melbourne, FL 32902  
TEL: (407) 724-7000  
FAX: (407) 724-7240  
4-7  
1...4567

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DG202CSE-T ROCHESTER QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO16, 0.150 INCH, MS-012AC, SOIC-16

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