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DG2032DN-T1-E3 PDF预览

DG2032DN-T1-E3

更新时间: 2024-11-27 14:27:39
品牌 Logo 应用领域
威世 - VISHAY 光电二极管输出元件
页数 文件大小 规格书
6页 86K
描述
SPDT, 2 Func, CMOS, PQCC12,

DG2032DN-T1-E3 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:QCCN, LCC12,.12SQ,20Reach Compliance Code:compliant
风险等级:5.84模拟集成电路 - 其他类型:SPDT
JESD-30 代码:S-PQCC-N12功能数量:2
端子数量:12最大通态电阻 (Ron):6.5 Ω
最高工作温度:85 °C最低工作温度:-40 °C
输出:SEPARATE OUTPUT封装主体材料:PLASTIC/EPOXY
封装代码:QCCN封装等效代码:LCC12,.12SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER
电源:3 V认证状态:Not Qualified
子类别:Multiplexer or Switches标称供电电压 (Vsup):3 V
表面贴装:YES最长接通时间:53 ns
切换:BREAK-BEFORE-MAKE技术:CMOS
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
Base Number Matches:1

DG2032DN-T1-E3 数据手册

 浏览型号DG2032DN-T1-E3的Datasheet PDF文件第2页浏览型号DG2032DN-T1-E3的Datasheet PDF文件第3页浏览型号DG2032DN-T1-E3的Datasheet PDF文件第4页浏览型号DG2032DN-T1-E3的Datasheet PDF文件第5页浏览型号DG2032DN-T1-E3的Datasheet PDF文件第6页 
DG2032  
Vishay Siliconix  
New Product  
High-Bandwidth, Low Voltage, Dual SPDT Analog Switch  
FEATURES  
BENEFITS  
APPLICATIONS  
D Single Supply (1.8 V to 5.5 V)  
D Low On-Resistance - rON: 2.4 W  
D Reduced Power Consumption  
D High Accuracy  
D Cellular Phones  
D Speaker Headset Switching  
D Audio and Video Signal Routing  
D PCMCIA Cards  
D Crosstalk and Off Isolation: -81 dB @  
D Reduce Board Space  
D Low-Voltage Logic Compatible  
D High Bandwidth  
1 MHz  
D QFN-12 (3 x 3 mm) Package  
D Low-Voltage Data Acquisition  
D ATE  
DESCRIPTION  
The DG2032 is a monolithic CMOS dual single-pole/  
double-throw (SPDT) analog switch. It is specifically designed  
for low-voltage, high bandwidth applications.  
power supply level when off. Break-before-make is  
guaranteed.  
With fast switching speeds, low on-resistance, high  
bandwidth, and low charge injection, the DG2032 is ideally  
suited for audio and video switching with high linearity.  
The DG2032’s on-resistance (3 W @ 2.7 V), matching and  
flatness are guaranteed over the entire analog voltage range.  
Wide dynamic performance is achieved with better than  
–80 dB for both cross-talk and off-isolation at 1 MHz.  
Built on Vishay Siliconix’s low voltage CMOS technology, the  
DG2032 contains an epitaxial layer which prevents latch-up.  
Both SPDT’s operate with independent control logic, conduct  
equally well in both directions and block signals up to the  
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION  
DG2032  
12-Pin QFN (3 X 3 mm)  
IN1 COM1 NC  
12  
11  
10  
TRUTH TABLE  
Logic  
NC1 and NC2  
NO1 and NO2  
NO1  
GND  
NO2  
NC1  
V+  
1
2
3
9
8
7
0
1
ON  
OFF  
ON  
OFF  
ORDERING INFORMATION  
NC2  
Temp Range  
Package  
Part Number  
-40 to 85°C  
12-Pin QFN (3 x 3 mm)  
DG2032DN  
4
5
6
IN2 COM2 NC  
Top View  
Document Number: 72387  
S-31650—Rev. A, 18-Aug-03  
www.vishay.com  
1
 

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