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DAC8803_15

更新时间： 2024-11-06 01:20:59
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德州仪器 - TI /
页数 文件大小 规格书
26页 2523K
描述
Quad, Serial Input 14-Bit Multiplying Digital-to-Analog Converter

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DAC8803  
www.ti.com  
SBAS340C–JANUARY 2005–REVISED FEBRUARY 2006  
Quad, Serial Input 14-Bit Multiplying Digital-to-Analog Converter  
FEATURES  
DESCRIPTION  
•
•
•
Relative Accuracy: 1 LSB Max  
The DAC8803 is a quad, 14-bit, current-output  
digital-to-analog converter (DAC) designed to operate  
from a single +2.7-V to 5-V supply.  
Differential Nonlinearity: 1 LSB Max  
2-mA Full-Scale Current  
with VREF = ±10 V  
0.5-µs Settling Time  
Midscale or Zero-Scale Reset  
The applied external reference input voltage VREF  
determines the full-scale output current. An internal  
feedback resistor (RFB) provides temperature tracking  
for the full-scale output when combined with an  
external I-to-V precision amplifier.  
•
•
•
Four Separate 4Q Multiplying Reference  
Inputs  
A
doubled buffered serial data interface offers  
•
•
•
Reference Bandwidth: 10 MHz  
high-speed, 3-wire, SPI and microcontroller  
compatible inputs using serial data in (SDI), clock  
(CLK), and a chip select (CS). In addition, a serial  
data out pin (SDO) allows for daisy chaining when  
Reference Dynamics: -105 dB THD  
SPI™-Compatible 3-Wire Interface:  
50-MHz  
•
•
•
•
•
Double Buffered Registers Enable  
Simultaneous Multichannel Update  
Internal Power-On Reset  
multiple  
packages  
are  
used.  
A
common  
level-sensitive load DAC strobe (LDAC) input allows  
simultaneous update of all DAC outputs from  
previously loaded input registers. Additionally, an  
internal power-on reset forces the output voltage to  
zero at system turn on. An MSB pin allows system  
reset assertion (RS) to force all registers to zero code  
when MSB = 0, or to half-scale code when MSB = 1.  
Compact SSOP-28 Package  
Industry-Standard Pin Configuration  
APPLICATIONS  
•
•
•
Automatic Test Equipment  
Instrumentation  
Digitally-Controlled Calibration  
The DAC8803 is packaged in an SSOP package.  
A
B C D  
V
REF  
D0  
D1  
R A  
FB  
SDO  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
D10  
D11  
D12  
D13  
A0  
Input  
Register  
DAC A  
Register  
DAC A  
DAC B  
DAC C  
DAC D  
I
A
OUT  
R
R
R
R
R
R
A
A
GND  
R
B
FB  
Input  
Register  
DAC B  
Register  
14  
I
C
OUT  
A
B
GND  
R
C
FB  
A1  
Input  
Register  
DAC C  
Register  
I
C
OUT  
SDI  
A
C
GND  
CLK  
EN  
CS  
R
D
FB  
Input  
Register  
DAC D  
Register  
I
D
OUT  
R
R
A
DAC  
B
C
D
A
D
GND  
2:4  
Power-On  
Reset  
A
F
GND  
Decode  
DGND  
RS  
MSB  
LDAC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SPI is a trademark of Motorola, Inc.  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2006, Texas Instruments Incorporated  
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