W180
Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
• Cypress PREMIS™ family offering
W180-01, 02, 03
Output
W180-51, 52, 53
Output
SS%
• Generates an EMI optimized clocking signal at the
output
0
1
Fin > Fout > Fin – 1.25% Fin + 0.625% > Fin > – 0.625%
Fin > Fout > Fin – 3.75% Fin + 1.875% > Fin > –1.875%
• Selectable output frequency range
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3V or 5V supply
• Low power CMOS design
Table 2. Frequency Range Selection
W180 Option#
-01, 51
(MHz)
-02, 52
(MHz)
-03, 53
(MHz)
• Available in 8-pin SOIC (Small Outline Integrated
Circuit)
FS2 FS1
0
0
1
1
0
1
0
1
8 < FIN < 10
8 < FIN < 10
N/A
Key Specifications
10 < FIN < 15 10 < FIN < 15
N/A
Supply Voltages:............................................VDD = 3.3V±5%
or VDD = 5V±10%
15 < FIN < 18
18 < FIN < 28
N/A
N/A
15 < FIN < 18
18 < FIN < 28
Frequency Range:...............................8 MHz < Fin < 28 MHz
Cycle to Cycle Jitter: ........................................300 ps (max.)
Selectable Spread Percentage:.................... 1.25% or 3.75%
Output Duty Cycle: ...............................40/60% (worst case)
Output Rise and Fall Time:...................................5 ns (max.)
Simplified Block Diagram
Pin Configurations
3.3V or 5.0V
SOIC
CLKIN or X1
NC or X2
GND
FS2
1
2
3
4
8
7
6
5
FS1
X1
VDD
XTAL
SS%
CLKOUT
Input
X2
Spread Spectrum
Output
W180
(EMI suppressed)
CLKIN or X1
NC or X2
GND
SSON#
FS1
1
2
3
4
8
7
6
5
VDD
SS%
CLKOUT
3.3V or 5.0V
Oscillator or
Reference Input
Spread Spectrum
W180
Output
(EMI suppressed)
Cypress Semiconductor Corporation
Document #: 38-07156 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 5, 2005