CYW181-53SX

更新时间： 2024-11-30 12:49:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	190K
描述
Peak-Reducing EMI Solution

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中文翻译

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数据手册

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CYW181-53SX 数据手册

W181

Peak-Reducing EMI Solution

• Integrated loop filter components

• Operates with a 3.3V or 5V supply

• Low-power CMOS design

• Available in 8-pin small outline integrated circuit

(SOIC) or 14-pin thin shrink small outline package

(TSSOP select options only)

Features

• Cypress PREMIS™ family offering

• Generates an EMI optimized clocking signal

at the output

• Selectable input to output frequency

• Single 1.25% or 3.75% down or center spread output

Simplified Block Diagram

Pin Configurations

3.3 or 5.0V

SOIC

CLKIN or X1

NC or X2

GND

FS2

FS1

VDD

CLKOUT

XTAL

Input

SS%

Spread Spectrum

Output

(EMI suppressed)

W181

40 MHz

Max.

CLKIN or X1

NC or X2

SSON#

FS1

GND

SS%

VDD

CLKOUT

3.3 or 5.0V

TSSOP

FS2

FS1

VDD

CLKOUT

CLKIN or X1

Oscillator or

NC or X2

GND

Reference Input

Spread Spectrum

Output

W181

(EMI suppressed)

SS%

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07152 Rev. *D

Revised July 06, 2004

12 3 4 5 6 7...9

中文翻译

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