Datasheet > 电信电路 > 网络接口> CYV15G0403DXB-BGXI

CYV15G0403DXB-BGXI

更新时间： 2024-01-22 07:26:18

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
45页	1145K
描述
Independent Clock Quad HOTLink II⑩ Transceiver

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CYV15G0403DXB-BGXI 数据手册

浏览型号CYV15G0403DXB-BGXI的Datasheet PDF文件第1页

浏览型号CYV15G0403DXB-BGXI的Datasheet PDF文件第3页

浏览型号CYV15G0403DXB-BGXI的Datasheet PDF文件第4页

浏览型号CYV15G0403DXB-BGXI的Datasheet PDF文件第5页

浏览型号CYV15G0403DXB-BGXI的Datasheet PDF文件第6页

浏览型号CYV15G0403DXB-BGXI的Datasheet PDF文件第7页

CYP15G0403DXB

CYV15G0403DXB

CYW15G0403DXB

Figure 1. HOTLink II™ System Connections

Serial Links

Independent

CYP(V)(W)15G0403DXB

Independent

CYP(V)(W)15G0403DXB

Serial Links

Backplane or

Cabled

Connections

Serial Links

The receive (RX) section of the CYP(V)(W)15G0403DXB

Quad HOTLink II consists of four independent byte-wide

channels. Each channel accepts a serial bit-stream from one

of two PECL-compatible differential line receivers, and using

a completely integrated Clock and Data Recovery PLL,

recovers the timing information necessary for data recon-

struction. Each recovered bit-stream is deserialized and

framed into characters, 8B/10B decoded, and checked for

transmission errors. Recovered decoded characters are then

written to an internal Elasticity Buffer, and presented to the

destination host system.

The parallel I/O interface may be configured for numerous

forms of clocking to provide the highest flexibility in system

architecture. In addition to clocking the transmit path with a

local reference clock, the receive interface may also be

configured to present data relative to a recovered clock or to a

local reference clock.

Each transmit and receive channel contains an independent

BIST pattern generator and checker. This BIST hardware

allows at-speed testing of the high-speed serial data paths in

each transmit and receive section, and across the intercon-

necting links.

The integrated 8B/10B encoder/decoder may be bypassed for

systems that present externally encoded or scrambled data at

the parallel interface.

The CYP(V)(W)15G0403DXB is ideal for port applications

where different data rates and serial interface standards are

necessary for each channel. Some applications include

multi-protocol routers, aggregation equipment, and switches.

Document #: 38-02065 Rev. *F

Page 2 of 45

[+] Feedback

123 4 5 6 7...45

下载PDF

与CYV15G0403DXB-BGXI相关器件

型号	品牌	描述	获取价格	数据表
CYV15G0403TB	CYPRESS	Independent Clock Quad HOTLink II⑩ Serializer	获取价格
CYV15G0403TB_09	CYPRESS	Independent Clock Quad HOTLink II Serializer	获取价格
CYV15G0403TB-BGC	CYPRESS	Independent Clock Quad HOTLink II⑩ Serializer	获取价格
CYV15G0403TB-BGXC	CYPRESS	Independent Clock Quad HOTLink II⑩ Serializer	获取价格
CYV15G0404DXB	CYPRESS	Independent Clock Quad HOTLink II⑩ Transceive	获取价格
CYV15G0404DXB_07	CYPRESS	Independent Clock Quad HOTLink II⑩ Transceive	获取价格