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CYV15G0404DXB-BGI PDF预览

CYV15G0404DXB-BGI

更新时间： 2024-11-28 03:01:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
43页 798K
描述
Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker

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中文翻译

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CYV15G0404DXB-BGI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：BGA-256
针数：256Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.88
数据速率：1500000 MbpsJESD-30 代码：S-PBGA-B256
JESD-609代码：e0长度：27 mm
功能数量：1端子数量：256
收发器数量：4最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HBGA封装等效代码：BGA256,20X20,50
封装形状：SQUARE封装形式：GRID ARRAY, HEAT SINK/SLUG
峰值回流温度（摄氏度）：225电源：3.3 V
认证状态：Not Qualified座面最大高度：1.745 mm
子类别：Network Interfaces最大压摆率：1.32 mA
标称供电电压：3.3 V表面贴装：YES
技术：BICMOS电信集成电路类型：ETHERNET TRANSCEIVER
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：27 mmBase Number Matches：1

CYV15G0404DXB-BGI 数据手册

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PRELIMINARY  
CYV15G0404DXB  
Independent Clock Quad HOTLink II™ Transceiver  
with Reclocker  
• Selectable input/output clocking options  
• Synchronous LVTTL parallel interface  
• JTAG boundary scan  
• Built-In Self-Test (BIST) for at-speed link testing  
• Per-channel Link Quality Indicator  
— Analog signal detect  
Features  
• Quadchanneltransceiverfor195-to1500-MBaudserial  
signaling rate  
— Aggregate throughput of up to 12 Gbits/second  
• Second-generation HOTLink® technology  
• Compliant to multiple standards  
— Digital signal detect  
• Low-power 3W @ 3.3V typical  
• Single 3.3V supply  
• 256-ball thermally enhanced BGA  
• 0.25µ BiCMOS technology  
• JTAG device ID ‘0C811069’x  
— SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre  
Channel, ESCON and Gigabit Ethernet (IEEE802.3z)  
—10 bit uncoded data or 8B/10B coded data  
• Truly independent channels  
— Each channel can perform reclocker function  
— Each channel can operate at a different signaling  
rate  
Functional Description  
—Each channel can transport a different data format  
The CYV15G0404DXB Independent Clock Quad HOTLink II™  
Transceiver is a point-to-point or point-to-multipoint communi-  
cations building block enabling transfer of data over a variety  
of high-speed serial links including SMPTE 292, SMPTE 259  
and DVB-ASI video applications. The signaling rate can be  
anywhere in the range of 195 to 1500 MBaud per serial link.  
Each channel operates independently with its own reference  
clock allowing different rates. Each transmit channel accepts  
parallel characters in an Input Register, encodes each  
character for transport, and then converts it to serial data.  
Each receive channel accepts serial data and converts it to  
parallel data, decodes the data into characters, and presents  
these characters to an Output Register. The received serial  
data can also be reclocked and retransmitted through the  
serial outputs. Figure 1 illustrates typical connections between  
independent video co-processors and corresponding  
CYV15G0404DXB chips.  
• Internal phase-locked loops (PLLs) with no external  
PLL components  
• Selectable differential PECL-compatible serial inputs  
per channel  
— Internal DC-restoration  
• Redundant differential PECL-compatible serial outputs  
per channel  
— No external bias resistors required  
— Signaling-rate controlled edge-rates  
—Source matched for 50Ω transmission lines  
• MultiFrame™ Receive Framer provides alignment  
options  
— Comma or Full K28.5 detect  
— Single or Multi-byte Framer for byte alignment  
— Low-latency option  
10  
10  
Serial Links  
10  
10  
10  
10  
Independent  
Channel  
CYV15G0404DXB  
10  
10  
Serial Links  
Serial Links  
10  
10  
Independent  
Channel  
CYV15G0404DXB  
10  
10  
Reclocker  
Reclocker  
10  
10  
Serial Links  
10  
10  
Cable  
Connections  
Figure 1. HOTLink II™ System Connections  
Cypress Semiconductor Corporation  
Document #: 38-02097 Rev. **  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised June 04, 2004  
1234567...43

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