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CYV15G0403TB-BGXC

更新时间： 2024-11-28 03:00:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟
页数 文件大小 规格书
21页 686K
描述
Independent Clock Quad HOTLink II⑩ Serializer

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CYV15G0403TB-BGXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, TBGA-256
针数：256Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.61JESD-30 代码：S-PBGA-B256
JESD-609代码：e1长度：27 mm
湿度敏感等级：3功能数量：1
端子数量：256最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.745 mm
标称供电电压：3.3 V表面贴装：YES
技术：BICMOS电信集成电路类型：TELECOM CIRCUIT
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：27 mmBase Number Matches：1

CYV15G0403TB-BGXC 数据手册

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CYV15G0403TB  
Independent Clock Quad HOTLink II™  
Serializer  
Features  
Functional Description  
• Second-generation HOTLink® technology  
The CYV15G0403TB Independent Clock Quad HOTLink II™  
Serializer is a point-to-point or point-to-multipoint communica-  
• Compliant to SMPTE 292M and SMPTE 259M video  
standards  
tions building block enabling transfer of data over a variety of  
high-speed serial links including SMPTE 292M and SMPTE  
259M video applications. It supports signaling rates in the  
range of 195 to 1500 Mbps per serial link. All four channels are  
independent and can simultaneously operate at different  
rates. Each channel accepts 10-bit parallel characters in an  
Input Register and converts them to serial data. Figure 1 illus-  
trates typical connections between independent video  
co-processors and corresponding CYV15G0403TB Serializer  
and CYV15G0404RB Reclocking Deserializer chips.  
• Quad channel video serializer  
— 195- to 1500-Mbps serial data signaling rate  
— Simultaneous operation at different signaling rates  
• Supports half-rate and full-rate clocking  
• Internal phase-locked loops (PLLs) with no external PLL  
components  
• Redundant differential PECL-compatible serial outputs per  
channel  
The CYV15G0403TB satisfies the SMPTE-259M and  
SMPTE-292M compliance as per SMPTE EG34-1999 Patho-  
logical Test Requirements.  
— No external bias resistors required  
— Signaling-rate controlled edge-rates  
— Internal source termination  
As  
a
second-generation  
HOTLink  
device,  
the  
CYV15G0403TB extends the HOTLink family with enhanced  
levels of integration and faster data rates, while maintaining  
serial-link compatibility (data and BIST) with other HOTLink  
devices. Each channel of the CYV15G0403TB Quad HOTLink  
II device independently accepts scrambled 10-bit transmission  
characters. These characters are serialized and output from  
dual Positive ECL (PECL) compatible differential trans-  
mission-line drivers at a bit-rate of either 10- or 20-times the  
input reference clock for that channel.  
• Synchronous LVTTL parallel interface  
• JTAG boundary scan  
• Built-In Self-Test (BIST) for at-speed link testing  
• Low-power 2W @ 3.3V typical  
• Single 3.3V supply  
• Thermally enhanced BGA  
• Pb-Free package option available  
• 0.25μ BiCMOS technology  
Each channel contains an independent BIST pattern  
generator. This BIST hardware allows at-speed testing of the  
high-speed serial data paths in each transmit section of this  
device, each receive section of a connected HOTLink II  
device, and across the interconnecting links.  
Figure 1. HOTLink II™ System Connections  
Reclocked  
Outputs  
10  
10  
10  
Independent  
Channel  
CYV15G0404RB  
10  
10  
Independent  
Channel  
CYV15G0403TB  
Serial Links  
10  
10  
Reclocking Deserializer  
Serializer  
10  
Reclocked  
Outputs  
Cypress Semiconductor Corporation  
Document #: 38-02104 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 2, 2007  
[+] Feedback  
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