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CYV15G0201DXB-BBXC

更新时间： 2024-02-16 10:49:32

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
46页	657K
描述
Dual-channel HOTLink II⑩ Transceiver

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中文翻译

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数据手册

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CYV15G0201DXB-BBXC 数据手册

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CYP15G0201DXB

CYV15G0201DXB

CYW15G0201DXB

Pin Descriptions CYP(V)(W)15G0201DXB Dual HOTLink II Transceiver (continued)

Pin Name I/O Characteristics

Signal Description

Decoder Mode Select. This input selects the behavior of the Decoder block.

DECMODE 3-Level Select^[4]

Static Control Input

When LOW, the Decoder is bypassed and raw 10-bit characters are passed to the Output

When MID, the Decoder is enabled and the Cypress Decoder table for Special Code

characters is used. When HIGH, the Decoder is enabled and the alternate Decoder table

for Special Code characters is used. See Table 25 for a list of the Special Codes supported

in both encoded modes.

RXMODE[1: 3-Level Select^[4]

Receive Operating Mode. These inputs are interpreted to select one of nine operating

Static Control Inputs modes of the receive path. See Table 13 for details.

RFEN

LVTTL input,

Reframe Enable for All Channels. Active HIGH. When HIGH, the framers in both channels

are enabled to frame per the presently enabled framing mode and selected framing

character.

Reframe Mode Select. Used to control the type of character framing used to adjust the

asynchronous,

internal pull-down

RFMODE

3-Level Select^[4]

Static Control Input character boundaries (based on detection of one or more framing characters in the received

serial bit stream). This signal operates in conjunction with the presently enabled channel

bonding mode, and the type of framing character selected.

When LOW, the low-latency framer is selected. This will frame on each occurrence of the

selected framing character(s) in the received data stream. This mode of framing stretches

the recovered clock for one or multiple cycles to align that clock with the recovered data.

When MID, the Cypress-mode multi-byte parallel framer is selected. This requires a pair of

the selected framing character(s), on identical 10-bit boundaries, within a span of 50 bits,

before the character boundaries are adjusted. The recovered character clock remains in the

same phasing regardless of character offset.

When HIGH, the alternate mode multi-byte parallel framer is selected. This requires

detection of the selected framing character(s) of the allowed disparities in the received serial

bit stream, on identical 10-bit boundaries, on four directly adjacent characters. The

recovered character clock remains in the same phasing regardless of character offset.

FRAMCHAR 3-Level Select^[4]

Framing Character Select. Used to control the character or portion of a character used for

Static Control Input character framing of the received data streams.

When MID, the framer looks for both positive and negative disparity versions of the 8-bit

Comma character. When HIGH, the framer looks for both positive and negative disparity

versions of the K28.5 character. Configuring FRAMCHAR to LOW is reserved for

component test.

Device Control Signals

PARCTL

3-Level Select^[4]

Parity Check/Generate Control. Used to control the different parity check and generate

Static Control Input functions.

When LOW, parity checking is disabled, and the RXOPx outputs are all disabled (High-Z).

When MID, and the Encoder/Decoder are enabled (TXMODE[1] ≠ LOW,

DECMODE ≠ LOW), TXDx[7:0] inputs are checked (along with TXOPx) for valid ODD parity,

and ODD parity is generated for the RXDx[7:0] outputs and presented on RXOPx. When

the Encoder and Decoder are disabled (TXMODE[1] = LOW, DECMODE = LOW), the

TXDx[7:0] and TXCTx[1:0] inputs are checked (along with TXOPx) for valid ODD parity, and

ODD parity is generated for the RXDx[7:0] and RXSTx[1:0] outputs and presented on

RXOPx. When HIGH, parity checking and generation are enabled. The TXDx[7:0] and

TXCTx[1:0] inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity is

generated for the RXDx[7:0] and RXSTx[2:0] outputs and presented on RXOPx.

Document #: 38-02058 Rev. *H

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与CYV15G0201DXB-BBXC相关器件

型号	品牌	描述	获取价格	数据表
CYV15G0201DXB-BBXI	CYPRESS	Dual-channel HOTLink II⑩ Transceiver	获取价格
CYV15G0203TB	CYPRESS	Independent Clock Dual HOTLink II Serializer	获取价格
CYV15G0203TB_07	CYPRESS	Independent Clock Dual HOTLink II⑩ Serializer	获取价格
CYV15G0203TB_09	CYPRESS	Independent Clock Dual HOTLink II Serializer	获取价格
CYV15G0203TB-BGC	CYPRESS	Independent Clock Dual HOTLink II Serializer	获取价格
CYV15G0203TB-BGXC	CYPRESS	Independent Clock Dual HOTLink II⑩ Serializer	获取价格
CYV15G0204RB	CYPRESS	Independent Clock Dual HOTLink II⑩ Reclocking	获取价格
CYV15G0204RB_09	CYPRESS	Independent Clock Dual HOTLink II Reclocking Deserializer	获取价格
CYV15G0204RB-BGC	CYPRESS	Independent Clock Dual HOTLink II⑩ Reclocking	获取价格
CYV15G0204RB-BGXC	CYPRESS	Independent Clock Dual HOTLink II⑩ Reclocking	获取价格
CYV15G0204TRB	CYPRESS	Independent Clock HOTLink II⑩ Dual Serializer	获取价格
CYV15G0204TRB-BGC	CYPRESS	Independent Clock HOTLink II⑩ Dual Serializer	获取价格
CYV15G0204TRB-BGXC	CYPRESS	Independent Clock HOTLink II⑩ Dual Serializer	获取价格
CYV15G0401DXB	CYPRESS	Quad HOTLink II Transceiver	获取价格
CYV15G0401DXB-BGC	CYPRESS	Quad HOTLink II Transceiver	获取价格
CYV15G0401DXB-BGI	CYPRESS	Quad HOTLink II Transceiver	获取价格
CYV15G0401DXB-BGXC	CYPRESS	Quad HOTLink II⑩ Transceiver	获取价格
CYV15G0401DXB-BGXI	CYPRESS	Quad HOTLink II⑩ Transceiver	获取价格
CYV15G0402DXB	CYPRESS	Quad HOTLink II⑩ SERDES	获取价格
CYV15G0402DXB-BGC	CYPRESS	Quad HOTLink II⑩ SERDES	获取价格

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