CYV15G0204RB
Independent Clock Dual HOTLink II™
Reclocking Deserializer
and SMPTE 259 video applications. It supports signaling rates
in the range of 195 to 1500 Mbps per serial link. The two
channels are independent and can simultaneously operate at
different rates. Each receive channel accepts serial data and
converts it to 10-bit parallel characters and presents these
characters to an Output Register. The received serial data can
also be reclocked and retransmitted through the reclocker
serial outputs. Figure 1 illustrates typical connections between
independent video co-processors and corresponding
Features
• Second-generation HOTLink® technology
• Compliant to SMPTE 292M and SMPTE 259M video
standards
• Dual-channel video reclocking deserializer
— 195- to 1500-Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
CYV15G0204RB
Reclocking
Deserializer
and
• Supportsreceptionofeither1.485or1.485/1.001Gbpsdata
rate with the same training clock
CYV15G0203TB Serializer chips.
The CYV15G0204RB satisfies the SMPTE-259M and
SMPTE-292M compliance as per SMPTE EG34-1999 Patho-
logical Test Requirements.
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL
components
As
a
second-generation HOTLink device, the
• Selectable differential PECL-compatible serial inputs
— Internal DC-restoration
CYV15G0204RB extends the HOTLink family with
enhanced levels of integration and faster data rates,
while maintaining serial-link compatibility (data and BIST)
with other HOTLink devices.
• Synchronous LVTTL parallel interface
• JTAG boundary scan
Each channel of the CYV15G0204RB Dual HOTLink II device
accepts a serial bit-stream from one of two selectable
PECL-compatible differential line receivers, and using a
completely integrated Clock and Data Recovery PLL, recovers
the timing information necessary for data reconstruction. The
recovered bit-stream is reclocked and retransmitted through
the reclocker serial outputs. Also, the recovered serial data is
deserialized and presented to the destination host system.
• Built-In Self-Test (BIST) for at-speed link testing
• Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power 2W @ 3.3V typical
• Single 3.3V supply
Each channel contains an independent BIST pattern checker.
This BIST hardware allows at-speed testing of the high-speed
serial data paths in each receive section of this device, each
transmit section of a connected HOTLink II device, and across
the interconnecting links.
• Thermally enhanced BGA
• Pb-Free package option available
• 0.25μ BiCMOS technology
Functional Description
The CYV15G0204RB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include
multi-format routers, switchers, format converters, SDI
monitors, and camera control units.
The CYV15G0204RB Independent Clock Dual HOTLink II™
Deserializing Reclocker is a point-to-point or point-to-multi-
point communications building block enabling transfer of data
over a variety of high-speed serial links including SMPTE 292
Figure 1. HOTLink II™ System Connections
Reclocked
Output
10
10
Independent
Channel
Independent
Channel
CYV15G0204RB
Serial Links
CYV15G0203TB
Serializer
Reclocking Deserializer
10
10
Reclocked
Output
Cypress Semiconductor Corporation
Document #: 38-02103 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 2, 2007
[+] Feedback
5秒后页面跳转
全球首块英伟达H200交付 黄仁勋“送货上门”
常用8脚开关电源芯片型号大全
74HC04芯片引脚图及功能、应用电路图讲解
CR6842芯片参数、引脚配置、应用电路图详解
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
