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CYPD2122-20FNXIT PDF预览

CYPD2122-20FNXIT

更新时间: 2024-11-05 15:40:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 外围集成电路
页数 文件大小 规格书
33页 2838K
描述
Microprocessor Circuit, CMOS, PBGA20, 1.63 X 2.03 MM, 0.55 MM HEIGHT, LEAD FREE, WLCSP-20

CYPD2122-20FNXIT 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:VFBGA,Reach Compliance Code:compliant
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.59JESD-30 代码:R-PBGA-B20
长度:2.03 mm端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
座面最大高度:0.55 mm最大供电电压:5.5 V
最小供电电压:2.7 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.4 mm端子位置:BOTTOM
宽度:1.63 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

CYPD2122-20FNXIT 数据手册

 浏览型号CYPD2122-20FNXIT的Datasheet PDF文件第2页浏览型号CYPD2122-20FNXIT的Datasheet PDF文件第3页浏览型号CYPD2122-20FNXIT的Datasheet PDF文件第4页浏览型号CYPD2122-20FNXIT的Datasheet PDF文件第5页浏览型号CYPD2122-20FNXIT的Datasheet PDF文件第6页浏览型号CYPD2122-20FNXIT的Datasheet PDF文件第7页 
EZ-PD™ CCG2 Datasheet  
USB Type-C Port Controller  
USB Type-C Port Controller  
General Description  
EZ-PD™ CCG2 is a USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG2 provides a  
complete USB Type-C and USB Power Delivery port control solution for passive cables, active cables, and powered accessories. It  
can also be used in many upstream and downstream facing port applications. EZ-PD CCG2 uses Cypress’s proprietary M0S8  
technology with a 32-bit, 48-MHz ARM® Cortex®-M0 processor with 32-KB flash and integrates a complete Type-C Transceiver  
including the Type-C termination resistors RP, RD and RA.  
Type-C Support  
Integrated transceiver (baseband PHY)  
Applications  
USB Type-C EMCA cables  
Integrated UFP (RD), EMCA (RA) termination resistors, and  
USB Type-C powered accessories  
current sources for DFP (RP)  
USB Type-C upstream facing ports  
Supports one USB Type-C port  
USB Type-C downstream facing ports  
Low-Power Operation  
2.7-V to 5.5-V operation  
Features  
Two independent VCONN rails with integrated isolation  
between the two  
32-bit MCU Subsystem  
48-MHz ARM Cortex-M0 CPU  
32-KB Flash  
Independent supply voltage pin for GPIO that allows 1.71-V to  
5.5-V signaling on the I/Os  
4-KB SRAM  
Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.0 mA  
In-system reprogrammable  
System-Level ESD on CC and VCONN Pins  
±8-kVContactDischargeand±15-kVAirGapDischargebased  
on IEC61000-4-2 level 4C  
Integrated Digital Blocks  
Integrated timers and counters to meet response times  
required by the USB-PD protocol  
Packages  
Run-time reconfigurable serial communication block (SCB)  
with reconfigurable I2C, SPI, or UART functionality  
1.63 mm × 2.03 mm, 20-ball wafer-level CSP (WLCSP) with  
0.4-mm ball pitch  
Clocks and Oscillators  
Integrated oscillator eliminating the need for external clock  
2.5 mm × 3.5 mm × 0.6 mm 14-pin DFN  
4.0 mm × 4.0 mm, 0.55 mm 24-pin QFN  
Supports industrial (40 °C to +85 °C) and extended industrial  
(40 °C to +105 °C) temperature ranges  
Logic Block Diagram  
CCG2: USB Type-C Cable Controller  
MCU Subsystem  
I/O Subsystem  
CC5  
Integrated Digital Blocks  
TCPWM1  
VCONN1  
SCB2  
(I2C, SPI, UART)  
CORTEX-M0  
48 MHz  
VCONN2  
SCB2  
(I2C, SPI, UART)  
VDDIO  
GPIO6  
Port  
Profiles and  
Configurations  
Flash  
(32 KB)  
Baseband MAC  
Baseband PHY  
4
SRAM  
(4 KB)  
Integrated Rd3, Ra  
,
7
and Rp  
Serial Wire Debug  
1 Timer, counter, pulse-width modulation block  
2 Serial communication block configurable as UART, SPI, or I2C  
3 Termination resistor denoting a UFP  
4 Termination resistor denoting an EMCA  
5 Configuration Channel  
6 General-purpose input/output  
7
Current Sources to indicate a DFP  
Cypress Semiconductor Corporation  
Document Number: 001-93912 Rev. *L  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 2, 2016  
 

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