Datasheet > CYPD2120-24LQXIT

CYPD2120-24LQXIT

更新时间： 2024-01-20 19:42:18

品牌	Logo	应用领域
英飞凌 - INFINEON		光电二极管外围集成电路
页数	文件大小	规格书
42页	665K
描述
EZ-PD™ CCG2 USB Type-C Port Controller

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CYPD2120-24LQXIT 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	HVQCCN,	Reach Compliance Code：	compliant
ECCN代码：	3A991.A.2	HTS代码：	8542.31.00.01
风险等级：	5.59	Is Samacsys：	N
JESD-30 代码：	S-XQCC-N24	长度：	4 mm
端子数量：	24	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	0.6 mm	最大供电电压：	5.5 V
最小供电电压：	2.7 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	4 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

CYPD2120-24LQXIT 数据手册

浏览型号CYPD2120-24LQXIT的Datasheet PDF文件第10页

EZ-PD™ CCG2 Datasheet

Timer/Counter/PWM Block (TCPWM)

Peripherals

EZ-PD CCG2 has six TCPWM blocks. Each implements a 16-bit

timer, counter, pulse-width modulator (PWM), and quadrature

decoder functionality. The block can be used to measure the

period and pulse width of an input signal (timer), find the number

of times a particular event occurs (counter), generate PWM

signals, or decode quadrature signals.

Serial Communication Blocks (SCB)

EZ-PD CCG2 has two SCBs, which can be configured to

implement an I²C, SPI, or UART interface. The hardware I²C

blocks implement full multi-master and slave interfaces capable

of multimaster arbitration. In the SPI mode, the SCB blocks can

be configured to act as master or slave.

GPIO

In the I²C mode, the SCB blocks are capable of operating at

speeds of up to 1 Mbps (Fast Mode Plus) and have flexible

buffering options to reduce interrupt overhead and latency for the

CPU. These blocks also support I²C that creates a mailbox

address range in the memory of EZ-PD CCG2 and effectively

reduce I²C communication to reading from and writing to an

array in memory. In addition, the blocks support 8-deep FIFOs

for receive and transmit which, by increasing the time given for

the CPU to read data, greatly reduce the need for clock

stretching caused by the CPU not having read data on time.

The I²C peripherals are compatible with the I²C Standard-mode,

Fast-mode, and Fast-mode Plus devices as defined in the NXP

I²C-bus specification and user manual (UM10204). The I²C bus

I/Os are implemented with GPIO in open-drain modes.

EZ-PD CCG2 has up to 10 GPIOs in addition to the I²C and SWD

pins, which can also be used as GPIOs. The I²C pins from SCB

0 are overvoltage-tolerant. The number of available GPIOs vary

with the package. The GPIO block implements the following:

■ Seven drive strength modes:

❐ Input only

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

The I²C port on SCB 1 block of EZ-PD CCG2 is not completely

■ Input threshold select (CMOS or LVTTL)

compliant with the I²C spec in the following respects:

■ Individual control of input and output buffer enabling/disabling

in addition to the drive strength modes

■ The GPIO cells for SCB 1's I²Cport arenot overvoltage-tolerant

and, therefore, cannot be hot-swapped or powered up

independently of the rest of the I²C system.

■ Hold mode for latching previous state (used for retaining I/O

state in Deep Sleep mode)

■ Fast-mode Plus has an I_OLspecification of 20 mA at a V_OLof

0.4 V. The GPIO cells can sink a maximum of 8-mA I_OLwith a

■ Selectable slew rates for dV/dt related noise control to improve

EMI

V_OLmaximum of 0.6 V.

During power-on and reset, the I/O pins are forced to the disable

state so as not to crowbar any inputs and/or cause excess

turn-on current. A multiplexing network known as a high-speed

I/O matrix is used to multiplex between various signals that may

connect to an I/O pin.

■ Fast-mode and Fast-mode Plus specify minimum Fall times,

which are not met with the GPIO cell; Slow strong mode can

help meet this spec depending on the bus load.

Document Number: 001-93912 Rev. *N

Page 6 of 41

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与CYPD2120-24LQXIT相关器件

型号	品牌	描述	获取价格	数据表
CYPD2121-24LQXIT	CYPRESS	Microprocessor Circuit, CMOS, 4 X 4 MM, 0.55 MM HEIGHT, LEAD FREE, MO-248, QFN-24	获取价格
CYPD2122-20FNXIT	INFINEON	EZ-PD™ CCG2 USB Type-C Port Controller	获取价格
CYPD2122-20FNXIT	CYPRESS	Microprocessor Circuit, CMOS, PBGA20, 1.63 X 2.03 MM, 0.55 MM HEIGHT, LEAD FREE, WLCSP-20	获取价格
CYPD2122-24LQXI	CYPRESS	Microprocessor Circuit, CMOS, 4 X 4 MM, 0.55 MM HEIGHT, LEAD FREE, MO-248, QFN-24	获取价格
CYPD2122-24LQXI	INFINEON	EZ-PD™ CCG2 USB Type-C Port Controller	获取价格
CYPD2122-24LQXIT	CYPRESS	Microprocessor Circuit, CMOS, 4 X 4 MM, 0.55 MM HEIGHT, LEAD FREE, MO-248, QFN-24	获取价格
CYPD2122-24LQXIT	INFINEON	EZ-PD™ CCG2 USB Type-C Port Controller	获取价格
CYPD2125-24LQXIT	CYPRESS	Microprocessor Circuit, CMOS, 4 X 4 MM, 0.55 MM HEIGHT, LEAD FREE, MO-248, QFN-24	获取价格
CYPD2134-24LQXI	CYPRESS	IC MCU 32BIT 32KB FLASH 24QFN	获取价格
CYPD2134-24LQXI	INFINEON	EZ-PD™ CCG2 USB Type-C Port Controller	获取价格
CYPD2134-24LQXIT	INFINEON	EZ-PD™ CCG2 USB Type-C Port Controller	获取价格
CYPD2134-24LQXIT	CYPRESS	Microprocessor Circuit, CMOS, 4 X 4 MM, 0.55 MM HEIGHT, LEAD FREE, MO-248, QFN-24	获取价格
CYPD2134-24LQXQ	CYPRESS	Microprocessor Circuit,	获取价格
CYPD2134-24LQXQT	CYPRESS	USB Type-C Port Controller	获取价格
CYPD2134A-24LQXQ	INFINEON	EZ-PD™ CCG2 USB Type-C Port Controller	获取价格
CYPD2134A-24LQXQT	INFINEON	EZ-PD™ CCG2 USB Type-C Port Controller	获取价格
CYPD2703-09FNXIT	INFINEON	EZ-PD™ CMG1 USB-C EMCA Controller	获取价格
CYPD2704-09FNXIT	INFINEON	EZ-PD™ CMG1 USB-C EMCA Controller	获取价格
CYPD2803A1-09FNXIT	INFINEON		获取价格
CYPD3120-40LQXI	CYPRESS	USB Type-C Port Controller	获取价格

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