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CYPD2120-24LQXIT PDF预览

CYPD2120-24LQXIT

更新时间: 2024-02-10 13:16:49
品牌 Logo 应用领域
英飞凌 - INFINEON 光电二极管外围集成电路
页数 文件大小 规格书
42页 665K
描述
EZ-PD™ CCG2 USB Type-C Port Controller

CYPD2120-24LQXIT 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:HVQCCN,Reach Compliance Code:compliant
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.59Is Samacsys:N
JESD-30 代码:S-XQCC-N24长度:4 mm
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
座面最大高度:0.6 mm最大供电电压:5.5 V
最小供电电压:2.7 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

CYPD2120-24LQXIT 数据手册

 浏览型号CYPD2120-24LQXIT的Datasheet PDF文件第2页浏览型号CYPD2120-24LQXIT的Datasheet PDF文件第3页浏览型号CYPD2120-24LQXIT的Datasheet PDF文件第4页浏览型号CYPD2120-24LQXIT的Datasheet PDF文件第6页浏览型号CYPD2120-24LQXIT的Datasheet PDF文件第7页浏览型号CYPD2120-24LQXIT的Datasheet PDF文件第8页 
EZ-PD™ CCG2 Datasheet  
EZ-PD CCG2 Block Diagram  
Figure 1. EZ-PD CCG2 Block Diagram  
CPU Subsystem  
CCG2  
SWD/TC  
SPCIF  
Cortex  
M0  
48 MHz  
FAST MUL  
FLASH  
32 KB  
SRAM  
4 KB  
SROM  
8 KB  
32-bit  
AHB-Lite  
Read Accelerator  
SRAM Controller  
SROM Controller  
NVIC, IRQMX  
System Resources  
Lite  
System Interconnect (Single Layer AHB)  
Peripheral Interconnect (MMIO)  
Power  
Sleep Control  
WIC  
Peripherals  
POR  
REF  
PCLK  
PWRSYS  
Clock  
Clock Control  
WDT  
USB-PD SS  
IMO  
ILO  
Reset  
Reset Control  
XRES  
Test  
DFT Logic  
DFT Analog  
Pads, ESD  
Power Modes  
Active/Sleep  
Deep Sleep  
High Speed I/O Matrix  
12 x GPIOs, 2 x OVTs  
I/O Subsystem  
input, which is made available to the user when it is not in use  
for system functions requested by the user.  
Functional Overview  
CPU and Memory Subsystem  
The CPU also includes a serial wire debug (SWD) interface,  
which is a 2-wire form of JTAG. The debug configuration used for  
EZ-PD CCG2 has four break-point (address) comparators and  
two watchpoint (data) comparators.  
CPU  
The Cortex-M0 CPU in EZ-PD CCG2 is part of the 32-bit MCU  
subsystem, which is optimized for low-power operation with  
extensive clock gating. It mostly uses 16-bit instructions and  
executes a subset of the Thumb-2 instruction set. This enables  
fully compatible binary upward migration of the code to higher  
performance processors such as the Cortex-M3 and M4, thus  
enabling upward compatibility. The Cypress implementation  
includes a hardware multiplier that provides a 32-bit result in one  
cycle. It includes a nested vectored interrupt controller (NVIC)  
block with 32 interrupt inputs and also includes a Wakeup  
Interrupt Controller (WIC). The WIC can wake the processor up  
from the Deep Sleep mode, allowing power to be switched off to  
the main processor when the chip is in the Deep Sleep mode.  
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)  
Flash  
The EZ-PD CCG2 device has a flash module with a flash  
accelerator, tightly coupled to the CPU to improve average  
access times from the flash block. The flash block is designed to  
deliver 1 wait-state (WS) access time at 48 MHz and with 0-WS  
access time at 24 MHz. The flash accelerator delivers 85% of  
single-cycle SRAM access performance on average. Part of the  
flash module can be used to emulate EEPROM operation if  
required.  
SROM  
Asupervisory ROM that contains boot and configuration routines  
is provided.  
Document Number: 001-93912 Rev. *N  
Page 4 of 41  

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