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CYP25G01K100V1-MGC PDF预览

CYP25G01K100V1-MGC

更新时间： 2024-11-07 20:08:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
44页 658K
描述
Telecom Circuit, 1-Func, PBGA456, 35 X 35 MM, 2.33 MM HEIGHT, BGA-456

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CYP25G01K100V1-MGC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：35 X 35 MM, 2.33 MM HEIGHT, BGA-456针数：456
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.92JESD-30 代码：S-PBGA-B456
JESD-609代码：e0长度：35 mm
功能数量：1端子数量：456
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA456,26X26,50封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：225
电源：1.5,1.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：2.46 mm子类别：ATM/SONET/SDH ICs
标称供电电压：3.3 V表面贴装：YES
电信集成电路类型：TELECOM CIRCUIT温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：35 mm
Base Number Matches：1

CYP25G01K100V1-MGC 数据手册

 浏览型号CYP25G01K100V1-MGC的Datasheet PDF文件第2页浏览型号CYP25G01K100V1-MGC的Datasheet PDF文件第3页浏览型号CYP25G01K100V1-MGC的Datasheet PDF文件第4页浏览型号CYP25G01K100V1-MGC的Datasheet PDF文件第5页浏览型号CYP25G01K100V1-MGC的Datasheet PDF文件第6页浏览型号CYP25G01K100V1-MGC的Datasheet PDF文件第7页 
2.5-Gbps Programmable Serial Interface™  
— Circuit board traces  
— Backplane links  
Features  
• High-speed (HS) Programmable Serial Interface™  
(PSI™)  
— Box-to-box links  
• 2.48- to 2.5-Gbps serial signaling rate  
• Full Bellcore and ITU jitter compliance  
• Flexible parallel-to-serial conversion in transmit path  
• Flexible serial-to-parallel conversion in receive path  
• Multiple selectable loopback/loop-through modes  
• 100K of usable gates of CPLD logic  
— Chip-to-chip communication  
• Extremely flexible clocking options  
— Four global clocks  
— Up to 192 additional product term clocks  
— Clock polarity at every register  
• Carry chain logic for fast and efficient arithmetic  
operations  
• JTAG programming interface with boundary scan  
support  
• 240K of integrated memory  
— 192K of synchronous or asynchronous SRAM  
— 48K of true Dual-Port or FIFO RAM  
• Power-saving mode  
• Supported standards:  
• Internal transmit and receive phase-locked loops  
(PLLs)  
• Logic dedicated Spread Aware PLL  
— SONET OC-48 and SDH STM-16  
• Transmit FIFO for flexible variable phase clocking  
• Differential CML serial input with internal termination  
and DC-restoration  
— InfiniBand™  
— Custom 2.5-Gbps interface  
• Differential CML serial output with source-matched  
impedance of 50Ω  
Development Software  
• Warp®  
• 240 user-programmable I/Os  
• Any Volt™ I/O interface  
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context  
— Programmable as 1.5V, 1.8V, 2.5V, 3.3V  
• Multiple I/O standards  
sensitive editing  
— Active-HDL FSM graphical finite state machine  
editor  
— LVCMOS, LVTTL, 3.3V PCI, SSTL2(I-II), SSTL3(I-II),  
HSTL(I-IV), and GTL+  
— Active-HDL SIM post-synthesis timing simulator  
— Architecture Explorer for detailed design analysis  
— Static Timing Analyzer for critical path analysis  
— Available on Windows® 9x, 2000, NT 4.0, XP, and ME  
— Supports all Cypress programmable logic products  
— Fully PCI-compliant (Rev. 2.2)  
• Direct interface to standard fiber-optic modules  
• Designed to drive:  
— Fiberoptic modules  
— Copper cables  
2.5-Gbps PSI Family—Standards Supported  
PSI Device  
CYS25G01K100  
CYP25G01K100  
SONET/SDH (OC48/STM16)  
InfiniBand  
Custom  
SONET/SDH  
High Speed  
X
X
X
X
2.5-Gbps PSI Family—General Features  
Cluster  
Channel  
Typical  
Gates  
Memory Memory  
Maximum User-  
Programmable I/O  
Device  
Macrocells (Kbits)  
(Kbits)  
Package Offering  
25G01K100 46K–144K  
1536 192  
48  
240  
456-BGA (35 × 35 mm, 1.27-mm pitch)  
2.5-Gbps PSI Family—Performance  
Logic Speed—  
Device  
Channels and Link Speed  
Total Bandwidth  
fMAX2(Logic)[1] (MHz)  
tPD Pin-to-Pin[1] (ns)  
25G01K100  
1 × 2.5 Gbps  
2.5 Gbps  
222  
7.5  
Note:  
1. See the section titled Switching Characteristics for definition.  
Cypress Semiconductor Corporation  
Document #: 38-02021 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised December 4, 2002  
1234567...44

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