Datasheet > CYPD1131-35FNXIT

CYPD1131-35FNXIT

更新时间： 2024-01-26 18:37:34

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		外围集成电路
页数	文件大小	规格书
31页	547K
描述
Microprocessor Circuit, CMOS, PBGA35, WLCSP-35

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CYPD1131-35FNXIT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	VFBGA,	Reach Compliance Code：	compliant
ECCN代码：	5A991.B.1	HTS代码：	8542.39.00.01
Factory Lead Time：	1 week	风险等级：	8.01
JESD-30 代码：	R-PBGA-B35	长度：	3.23 mm
端子数量：	35	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	VFBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	0.55 mm	最大供电电压：	5.5 V
最小供电电压：	1.8 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	BALL
端子节距：	0.4 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	2.1 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

CYPD1131-35FNXIT 数据手册

CCG1 Datasheet

USB Type-C Port Controller with Power

Delivery

General Description

CCG1 provides a complete USB Type-C and USB Power Delivery port control solution. The core architecture of CCG1 enables a

base Type-C solution that can scale to a complete 100-W USB Power Delivery with Alternate Mode multiplex support. CCG1 is also

a Type-C cable ID IC for active and passive cables. The CCG1 controller detects connector insert, plug orientation and VCONN

switching signals. CCG1 makes it easier to add USB Power Delivery to any architecture because it provides control signals to manage

external VBUS and V_CONNpower management solutions and external mux controls for most single cable-docking solutions.

The CCG1 family of devices are fixed-function parts that use a configuration table to control their operation in different applications.

The functionality is implemented in firmware and will be certified against USB Implementers Forum (USB-IF) compliance tests when

available. The programmability allows CCG1 devices to track any USB Specification changes. For information on accessing the source

code, contact Cypress support.

Type-C Support

■ Integrated transceiver (BB PHY)

Applications

■ Notebooks, tablets, monitors, docking stations

■ Supports up to two USB ports with PD

■ Power adapters, USB Type-C cables

■ Supports routing of all protocols through an external mux

Features

PD Support

■ Supports Provider and Consumer roles

32-bit MCU Subsystem

■ 48-MHz ARM Cortex-M0 CPU with 32-KB flash and 4-KB

■ Supports all power profiles

SRAM

Low-Power Operation

■ 3.2 V to 5.5 V operation

■ Sleep 1.3 mA, Deep Sleep 1.3 A^[1]

Packages

Integrated analog blocks

■ 12-bit, 1-Msps ADC for VBUS voltage and current monitoring

■ Dynamic overcurrent and overvoltage protection

Integrated digital blocks

■ 40-pin QFN

■ Two configurable 16-bit TCPWM blocks

■ One I²C master or slave

■ 16-pin SOIC

■ 35-ball wafer-level CSP (WLCSP)

Figure 1. CCG1 Block Diagram^{[2, 3, 4, 5, 6, 7]}

Notes

1. Values measured for CCG1 silicon only. Application specific power numbers may be higher.

2. Timer, counter, pulse-width modulation block.

3. Serial communication block configurable as I C.

4. Base band.

5. Termination resistor denoting a Downstream Facing Port (DFP).

6. Termination resistor denoting a Upstream Facing Port (UFP).

7. Termination resistor denoting an Electronically Marked Cable Assembly (EMCA).

Cypress Semiconductor Corporation

Document Number: 001-93639 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 3, 2017

12 3 4 5 6 7...31

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