PRELIMINARY
CYP15G0401RB
Pin Descriptions (continued)
CYP15G0401RB Quad HOTLink II Receiver
Pin Name
I/O Characteristics
Signal Description
RXLE
LVTTL Input,
asynchronous,
internal pull-up
Receive Channel Power-control Latch Enable. Active HIGH. When RXLE = HIGH, the
signals on the BRE[3:0] inputs directly control the power enables for the receive PLLs
and analog circuitry. When the BRE[3:0] input is HIGH, the associated receive channel
A through D PLL and analog circuitry are active. When the BRE[3:0] input is LOW, the
associated receive channel A through D PLL and analog circuitry are powered down. The
specific mapping of BRE[3:0] signals to the associated receive channel enables is listed
in Table 2. When RXLE returns LOW, the last values present on BRE[3:0] are captured
in the internal RX PLL Enable Latch. When the device is reset (TRSTZ = LOW), the latch
is reset to disable all receive channels.
BRE[3:0] LVTTL Input,
asynchronous,
BIST and Receive Channel Enables. These inputs are passed to and through the BIST
Enable Latch when BISTLE is HIGH, and captured in this latch when BISTLE returns
LOW. These inputs are passed to and through the Receive Channel Enable Latch when
RXLE is HIGH, and captured in this latch when RXLE returns LOW.
internal pull-up
LFIA
LFIB
LFIC
LFID
LVTTL Output,
Asynchronous
Link Fault Indication Output. Active LOW. LFIx is the logical OR of four internal condi-
tions:
1. Received serial data frequency outside expected range
2. Analog amplitude below expected levels
3. Transition density lower than expected
4. Receive Channel disabled.
JTAG Interface
TMS
LVTTL Input,
internal pull-up
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high
for ≥5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset
automatically upon application of power to the device.
TCLK
TDO
LVTTL Input,
internal pull-down
JTAG Test Clock
Three-state
LVTTL Output
Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not
selected.
TDI
LVTTL Input, internal pull-up Test Data In. JTAG data input port.
Power
V
+3.3V Power
CC
GND
Signal and power ground for all internal circuits.
family, not limited to 100K PECL) or AC-coupled to +5V
powered optical modules. The common-mode tolerance of
these line receivers accommodates a wide range of signal
termination voltages. Each receiver provides internal
DC-restoration, to the center of the receiver’s common mode
range, for AC-coupled signals.
CYP15G0401RB HOTLink II Operation
The CYP15G0401RB is a highly configurable device designed
to support reliable transfer of large quantities of data, using
high-speed serial links, from one or multiple sources to one
destination. This device supports four single-byte or
single-character channels.
Signal Detect/Link Fault
CYP15G0401RB Receive Data Path
Each selected Line Receiver (i.e., that routed to the clock and
data recovery PLL) is simultaneously monitored for
Serial Line Receivers
• analog amplitude above limit specified by SDASEL
• transition density greater than specified limit
Two differential Line Receivers, INx1
± and INx2±, are
available on each channel for accepting serial data streams.
The active Serial Line Receiver on a channel is selected using
the associated INSELx input. The Serial Line Receiver inputs
are differential, and can accommodate wire interconnect and
filtering losses or transmission line attenuation greater than
16 dB. For normal operation, these inputs should receive a
• range controller reports the received data stream within
[4]
normal frequency range (±1500 ppm)
• receive channel enabled
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each
receive channel.
signal of at least VI
> 100 mV, or 200 mV peak-to-peak
DIFF
differential. Each Line Receiver can be DC- or AC-coupled to
+3.3V powered fiber-optic interface modules (any ECL/PECL
Document #: 38-02111 Rev. **
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