PRELIMINARY
CYP15G0401RB
Pin Descriptions
CYP15G0401RB Quad HOTLink II Receiver
Pin Name
I/O Characteristics
Signal Description
Receive Path Data Signals
RXDA[7:0] LVTTL Output,
RXDB[7:0] synchronous to the
Parallel Data Output. These outputs change following the rising edge of the selected
receive interface clock.
RXDC[7:0] selectedRXCLKx↑output
When the Decoder is enabled (DECMODE = HIGH or MID), these outputs represent
either received data or special characters. The status of the received data is represented
by the values of RXSTx[2:0].
[2]
RXDD[7:0] (or TRGCLK
↑ input
when RXCKSEL = LOW)
When the Decoder is bypassed (DECMODE = LOW), RXDx[7:0] become the higher order
bits of the 10-bit received character. See Table 7 for details.
RXSTA[2: LVTTL Output,
0] synchronous to the
RXSTB[2: selectedRXCLKx output
Parallel Status Output. These outputs change following the rising edge of the selected
receive interface clock.
↑
When the Decoder is bypassed (DECMODE = LOW), RXSTx[1:0] become the two
low-order bits of the 10-bit received character, while RXSTx[2] = HIGH indicates the
presence of a Comma character in the Output Register. See Table 7 for details.
[2]
0]
(or TRGCLK↑ input
RXSTC[2: when RXCKSEL = LOW)
0]
When the Decoder is enabled (DECMODE = HIGH or MID), RXSTx[2:0] provide status
of the received signal. See Table 9 and Table 10 for a list of Receive Character status.
RXSTD[2:
0]
RXOPA
RXOPB
RXOPC
RXOPD
Three-state, LVTTL
Output, synchronous to parity output at these pins is valid for the data on the associated RXDx bus bits. When
the selected parity generation is disabled (PARCTL = LOW) these output drivers are disabled (High-Z).
RXCLKx output
(or TRGCLK input
when RXCKSEL = LOW)
Receive Path Odd Parity. When parity generation is enabled (PARCTL ≠ LOW), the
↑
[2]
↑
Receive Path Clock and Clock Control
RXRATE LVTTLInput,staticcontrol Receive Clock Rate Select. When LOW, the RXCLKx± recovered clock outputs are
input, internal pull-down complementary clocks operating at the recovered character rate. Data for the associated
receive channels should be latched on the rising edge of RXCLKx+ or falling edge of
RXCLKx–.
When HIGH, the RXCLKx± recovered clock outputs are complementary clocks operating
at half the character rate. Data for the associated receive channels should be latched
alternately on the rising edge of RXCLKx+ and RXCLKx–.
When TRGCLK± is selected to clock the output registers (RXCKSELx = LOW), RXRATEx
is not interpreted. The RXCLKA± and RXCLKC± output clocks will follow the frequency
and duty cycle of TRGCLK±.
TRGRATE LVTTL Input,
Training Clock Rate Select. When TRGCLK is selected to clock the receive parallel
interfaces (RXCKSEL = LOW), the TRGRATE input also determines if the clocks on the
static control input,
internal pull-down
RXCLKA
± and RXCLKC± outputs are full or half-rate. When TRGRATE = HIGH
(TRGCLK is half-rate) and RXCKSEL = LOW, the RXCLKA± and RXCLKC± output clocks
are also half-rate clocks and follow the frequency and duty cycle of the TRGCLK input.
When TRGRATE = LOW (TRGCLK is full-rate) and RXCKSEL = LOW, the RXCLKA± and
RXCLKC± output clocks are full-rate clocks and follow the frequency and duty cycle of
the TRGCLK input.
[3]
FRAMCH Three-level Select
,
Framing Character Select. Used to select the character or portion of a character used
for character framing of the received data streams. When MID, the Framer looks for both
positive and negative disparity versions of the eight-bit Comma character. When HIGH,
the Framer looks for both positive and negative disparity versions of the K28.5 character.
Configuring FRAMCHAR to LOW is reserved for component test.
AR
static control input
RFEN
LVTTL Input,
asynchronous,
internal pull-down
Reframe Enable for All Channels. Active HIGH. When HIGH, the framers in all four
channels are enabled to frame per the presently enabled framing mode as selected by
RFMODE and selected framing character as selected by FRAMCHAR.
Notes:
2. When TRGCLK is configured for half-rate operation (TRGRATE = HIGH), these inputs are sampled (or the outputs change) relative to both the rising and falling
edges of TRGCLK.
3. Three-level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and
HIGH. The LOW level is usually implemented by direct connection to V (ground). The HIGH level is usually implemented by direct connection to V . When
SS
CC
not connected or allowed to float, a Three-level select input will self-bias to the MID level.
Document #: 38-02111 Rev. **
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