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CYI9531OXC

更新时间: 2024-11-24 02:54:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器外围集成电路光电二极管PC
页数 文件大小 规格书
10页 234K
描述
PCIX I/O System Clock Generator with EMI Control Features

CYI9531OXC 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SSOP包装说明:SSOP, SSOP28,.3
针数:28Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.49JESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:10.2 mm
湿度敏感等级:3端子数量:28
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:133.3 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP28,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
主时钟/晶体标称频率:33.3 MHz认证状态:Not Qualified
座面最大高度:2 mm子类别:Clock Generators
最大压摆率:300 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:5.3 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

CYI9531OXC 数据手册

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C9531  
PCIX I/O System Clock Generator with EMI  
Control Features  
Table 1. Test Mode Logic Table[1]  
Features  
Input Pins  
S1  
Output Pins  
• Dedicated clock buffer power pins for reduced noise,  
crosstalk and jitter  
OE  
S0  
LOW  
HIGH  
LOW  
HIGH  
X
CLK  
XIN  
2 * XIN  
3 * XIN  
4 * XIN  
REF  
XIN  
XIN  
XIN  
XIN  
• Input clock frequency of 25 MHz to 33 MHz  
• Output frequencies of XINx1, XINx2, XINx3 and XINx4  
• One output bank of five clocks  
HIGH  
HIGH  
HIGH  
HIGH  
LOW  
LOW  
LOW  
HIGH  
HIGH  
X
• One REF XIN clock output  
• SMBus clock control interface for individual clock  
Three-state Three-state  
disabling and SSCG control  
• Output clock duty cycle is 50% (± 5%)  
• < 250 ps skew between output clocks within a bank  
• Output jitter <175 ps  
• Spread Spectrum feature for reduced electromagnetic  
interference (EMI)  
• OE pin for entire output bank enable control and  
testability  
• 28-pin SSOP and TSSOP packages  
Block Diagram  
Pin Configuration  
28  
REF  
VDD  
1
2
3
4
5
6
7
8
SDATA  
SCLK  
VSS  
27  
26  
25  
SSCG  
CLK0  
SSCG#  
Logic  
XIN  
XOUT  
VSS  
CLK1  
CLK2  
/N  
VDDP  
CLK0  
CLK1  
CLK2  
VSS  
VDDP  
CLK3  
CLK4  
VDDA  
VSS  
1
0
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
CLK3  
S0  
S1  
GOOD#  
VSS  
IA0  
IA1  
IA2  
VDDA  
OE  
CLK4  
XIN  
OE  
GOOD#  
XOUT  
9
REF  
10  
11  
12  
13  
14  
SDATA  
SCLK  
IA(0:2)  
I2C  
Control  
Logic  
SSCG#  
S(0,1)  
Note:  
1. XIN is the frequency of the clock on the device’s XIN pin.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07034 Rev. *E  
Revised August 30, 2004  

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