Datasheet > CYIA2SC0300AA-BQE

CYIA2SC0300AA-BQE

更新时间： 2024-02-04 05:07:36

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		传感器图像传感器
页数	文件大小	规格书
18页	735K
描述
1/3” VGA-Format CMOS Image Sensor

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技术参数
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CYIA2SC0300AA-BQE 技术参数

生命周期：	Obsolete	Reach Compliance Code：	unknown
风险等级：	5.84	主体宽度：	11.4 mm
主体高度：	2.28 mm	主体长度或直径：	12.5 mm
动态范围：	120 dB	外壳：	CERAMIC
安装特点：	SURFACE MOUNT	光学格式：	1/3 inch
输出类型：	DIGITAL OUTPUT	封装形状/形式：	RECTANGULAR
像素大小：	8X8 µm	传感器/换能器类型：	IMAGE SENSOR,CMOS
表面贴装：	YES	端接类型：	SOLDER

CYIA2SC0300AA-BQE 数据手册

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CYIA2SC0300AA-BQE

1/3” VGA-Format CMOS Image Sensor

Features

Sensor Architecture

The diagram in Figure 1 shows the major functional blocks of

the imager. These blocks include:

• VGA Resolution

• 1/3” Optical Format

• Automotive Grade device

• 120 db Dynamic Range

• 60 PIN CBGA

• Image sensor array

• Row control circuitry

• Column sense circuitry

• Analog-to-digital converters

• Timing and control logic

• Program registers

• Low power dissipation

Functional Description

Cypress IM103 is Automotive grade CMOS Image Sensor with

• Digital-output shift registers

high dynamic range (120 db). IM103 is built with Autobrite

Sensor array: The sensor array consists of an optically active

482 row X 642 column matrix, with 18 additional dark columns

on right side of the array (the array is described more fully in

section 3). Each sensing element (pixel) is 8 µm X 8 µm in size.

technology useful for Automotive Vision Systems which

produce crisp clear video in visible and near IR wavelengths.

Device can be used for Lane departure working, Night Vision,

Adaptive Cruise control, driver drowsiness etc.

Timing and control circuitry: The sensor uses two clocks

(data strobe or DSTR, and system clock or SCLK). Data strobe

controls the timing of the output shift registers, while SCLK

controls exposure and data conversion timing. Clocking

details are given in section 5.

Introduction

This document describes the automotive grade IM103 1/3”

format VGA CMOS image sensor. The description covers:

• Architecture

• Operation

Column circuitry: The column circuitry includes a column

amplifier (with correlated double sampling [CDS] capability)

and a 12-bit analog-to-digital converter (ADC). Multiple ADCs

operate in parallel across the array.

• Wide-dynamic-range capture

• Register settings

• Electrical and electro-optical specifications

Output registers: Data from the ADCs are shifted into a

parallel-in/serial-out 24-bit-wide row buffer. Data are shifted

out to the parallel data I/O from the buffer after each row of

data is converted.

This imager chip can be supplied in several different

configurations including:

• Monochrome or color pixel array

Sensor Array

ROW

SCLK

Column Amplifiers/CDS

Analog/Digital Converters

RESET

Data Shift Registers

DSTR

Figure 1. IM103 Image Sensor Block Diagram.

Cypress Semiconductor Corporation

Document #: 001-11358 Rev. **

•

198 Champion Court

•

San Jose, CA 95134-1709

•

Revised October 13, 2006

408-943-2600

12 3 4 5 6 7...18

中文翻译

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