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CYI9531OXCT

更新时间： 2024-02-26 12:31:13

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器 PC
页数	文件大小	规格书
10页	234K
描述
PCIX I/O System Clock Generator with EMI Control Features

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中文翻译

获取价格

数据手册

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CYI9531OXCT 数据手册

C9531

PCIX I/O System Clock Generator with EMI

Control Features

Table 1. Test Mode Logic Table^[1]

Features

Input Pins

Output Pins

• Dedicated clock buffer power pins for reduced noise,

crosstalk and jitter

LOW

HIGH

LOW

HIGH

CLK

XIN

2 * XIN

3 * XIN

4 * XIN

REF

XIN

• Input clock frequency of 25 MHz to 33 MHz

• Output frequencies of XINx1, XINx2, XINx3 and XINx4

• One output bank of five clocks

HIGH

LOW

HIGH

• One REF XIN clock output

• SMBus clock control interface for individual clock

Three-state Three-state

disabling and SSCG control

• Output clock duty cycle is 50% (± 5%)

• < 250 ps skew between output clocks within a bank

• Output jitter <175 ps

• Spread Spectrum feature for reduced electromagnetic

interference (EMI)

• OE pin for entire output bank enable control and

testability

• 28-pin SSOP and TSSOP packages

Block Diagram

Pin Configuration

REF

VDD

SDATA

SCLK

VSS

SSCG

CLK0

SSCG#

Logic

XIN

XOUT

VSS

CLK1

CLK2

VDDP

CLK0

CLK1

CLK2

VSS

VDDP

CLK3

CLK4

VDDA

VSS

CLK3

GOOD#

VSS

IA0

IA1

IA2

VDDA

CLK4

XIN

GOOD#

XOUT

REF

SDATA

SCLK

IA(0:2)

I²C

Control

Logic

SSCG#

S(0,1)

Note:

1. XIN is the frequency of the clock on the device’s XIN pin.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07034 Rev. *E

Revised August 30, 2004

12 3 4 5 6 7...10

中文翻译

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