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CY8C4127AZI-M485 PDF预览

CY8C4127AZI-M485

更新时间: 2024-11-06 00:51:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
41页 3734K
描述
Programmable System-on-Chip

CY8C4127AZI-M485 数据手册

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PSoC® 4: PSoC 4100M Family  
Datasheet  
Programmable System-on-Chip (PSoC®)  
General Description  
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an  
ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The  
PSoC 4100M product family, based on this platform architecture, is a combination of a microcontroller with digital programmable logic,  
programmable analog, programmable interconnect, high-performance analog-to-digital conversion, opamps with comparator mode,  
and standard communication and timing peripherals. The PSoC 4100M products will be fully compatible with members of the PSoC 4  
platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning  
of the design.  
Features  
32-bit MCU Subsystem  
Serial Communication  
24-MHz ARM Cortex-M0 CPU with single-cycle multiply  
Up to 128 kB of flash with Read Accelerator  
Up to 16 kB of SRAM  
Four independent run-time reconfigurable serial  
communication blocks (SCBs) with reconfigurable I2C, SPI, or  
UART functionality  
Timing and Pulse-Width Modulation  
DMA engine  
Eight 16-bit timer/counter pulse-width modulator (TCPWM)  
blocks  
Programmable Analog  
Four opamps that operate in Deep Sleep mode at very low  
current levels  
Center-aligned, Edge, and Pseudo-random modes  
All opamps have reconfigurable high current pin-drive,  
high-bandwidth internal drive, ADC input buffering, and  
Comparator modes with flexible connectivity allowing input  
connections to any pin  
Comparator-based triggering of Kill signals for motor drive and  
other high-reliability digital logic applications  
Package Options  
Four current DACs (IDACs) for general-purpose or capacitive  
sensing applications on any pin  
68-pin QFN, 64-pin TQFP wide and narrow pitch, and 48-pin  
and 44-pin TQFP packages  
Two low-power comparators that operate in Deep Sleep mode  
12-bit SAR ADC with 806-Ksps conversion rate  
Up to 55 programmable GPIOs  
GPIO pins can be CapSense, LCD, analog, or digital  
Drive modes, strengths, and slew rates are programmable  
Low Power 1.71 to 5.5 V Operation  
20-nA Stop Mode with GPIO pin wakeup  
Extended Industrial Temperature Operation  
Hibernate and Deep Sleep modes allow wakeup-time versus  
power trade-offs  
–40 °C to +105 °C operation  
Capacitive Sensing  
PSoC Creator Design Environment  
Cypress Capacitive Sigma-Delta (CSD) technique provides  
best-in-class SNR (>5:1) and water tolerance  
Integrated Development Environment (IDE) provides  
schematic design entry and build (with analog and digital  
automatic routing)  
Cypress-supplied software component makes capacitive  
sensing design easy  
Applications Programming Interface (API component) for all  
fixed-function and programmable peripherals  
Automatic hardware tuning (SmartSense™)  
Segment LCD Drive  
Industry-Standard Tool Compatibility  
LCD drive supported on all pins (common or segment)  
Operates in Deep Sleep mode with 4 bits per pin memory  
After schematic entry, development can be done with  
ARM-based industry-standard development tools  
Cypress Semiconductor Corporation  
Document Number: 001-96519 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 19, 2016  

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