Automotive PSoC® 4:
PSoC 4100S Plus Datasheet
Programmable System-on-Chip (PSoC)
Programmable System-on-Chip (PSoC)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
Arm® Cortex™-M0+ CPU while being AEC-Q100 compliant. It combines programmable and reconfigurable analog and digital blocks
with flexible automatic routing. PSoC 4100S Plus is a member of the PSoC 4 platform architecture. It is a combination of a microcon-
troller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class perfor-
mance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity.
PSoC 4100S Plus products will be upward compatible with members of the PSoC 4 platform for new applications and design needs.
■ Timing and Pulse-Width Modulation
❐ Eight 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks
Features
■ Automotive Electronics Council (AEC) AEC-Q100 Qualified
❐ Center-aligned, Edge, and Pseudo-random modes
❐ Comparator-based triggering of Kill signals for motor drive
and other high-reliability digital logic applications
■ 32-bit MCU Subsystem
❐ 48-MHz Arm Cortex-M0+ CPU
❐ Up to 128 KB of flash with Read Accelerator
❐ Up to 16 KB of SRAM
❐ Quadrature decoder
■ Clock Sources
❐ 8-channel DMA engine
❐ 4 to 33 MHz external crystal oscillator (ECO)
❐ PLL to generate 48-MHz frequency
❐ 32-kHz Watch Crystal Oscillator (WCO)
❐ ±2% Internal Main Oscillator (IMO)
❐ 32-kHz Internal Low-power Oscillator (ILO)
■ Programmable Analog
❐ Two opamps with reconfigurable high-drive external and
high-bandwidth internal drive and Comparator modes and
ADC input buffering capability. Opamps can operate in Deep
Sleep low-power mode.
❐ 12-bit 1-Msps SAR ADC with differential and single-ended
modes, and Channel Sequencer with signal averaging
■ True Random Number Generator (TRNG)
❐ TRNG generates truly random number for secure key gen-
eration for Cryptography applications
❐ Single-slope 10-bit ADC function provided by a capacitance
sensing block
❐ Two current DACs (IDACs) for general-purpose or capacitive
■ CAN Block
sensing applications on any pin
❐ CAN 2.0B block with support for Time-Triggered CAN
(TTCAN)
❐ Two low-power comparators that operate in Deep Sleep
low-power mode
■ Temperature Range
■ Programmable Digital
❐ Programmable logic blocks allowing Boolean operations to
be performed on port inputs and outputs
❐ Grade-A: –40 °C to +85 °C
❐ Grade-S: –40 °C to +105 °C
❐ Grade-E: –40 °C to +125 °C[1]
■ Low-Power 1.71 V to 5.5 V Operation
❐ Deep Sleep mode with operational analog and 2.5 A digital
system current
■ Up to 54 Programmable GPIO Pins
❐ 40-pin QFN and 64-pin TQFP packages[2]
❐ Any GPIO pin can be CapSense, analog, or digital
❐ Drive modes, strengths, and slew rates are programmable
■ Capacitive Sensing
❐ Cypress CapSense Sigma-Delta (CSD) provides
best-in-class signal-to-noise ratio (SNR) (> 5:1) and water
tolerance
❐ Cypress-supplied software component makes capacitive
sensing design easy
■ PSoC Creator Design Environment
❐ Integrated Development Environment (IDE) provides schematic
design entry and build (with analog and digital automatic routing)
❐ Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
❐ Automatic hardware tuning (SmartSense™)
■ Industry-Standard Tool Compatibility
■ LCD Drive Capability
❐ After schematic entry, development can be done with
Arm-based industry-standard development tools
❐ LCD segment drive capability on GPIOs
■ Serial Communication
❐ Five independent run-time reconfigurable Serial Communi-
cation Blocks (SCBs) with re-configurable I2C, SPI, UART
functionality, or LIN Slave functionality
Notes
1. Grade-E specifications (at +125 °C) are preliminary. Contact Cypress for the availability of Grade-E devices.
2. 40-pin QFN package specifications are preliminary. Contact Cypress for the availability of 40-pin QFN package devices.
Cypress Semiconductor Corporation
Document Number: 002-20072 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 4, 2019
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