CY8C23433, CY8C23533
PSoC Functional Overview
Digital System
The PSoC family consists of many programmable
system-on-chips with on-chip controller devices. These devices
are designed to replace multiple traditional MCU-based system
components with a low-cost single-chip programmable device.
PSoC devices include configurable blocks of analog and digital
logic, and programmable interconnects. This architecture make
it possible for you to create customized peripheral configurations
that match the requirements of each individual application.
additionally, a fast central processing unit (CPU), flash memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts and packages.
The Digital system consists of 4 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user module references.
Figure 1. Digital System Block Diagram
Port 3
Port 2
Port 1
Port 0
To SystemBus
DigitalClocks
FromCore
ToAnalog
System
The PSoC architecture, as shown in the Logic Block Diagram on
page 1, consists of four main areas: PSoC core, digital system,
analog system, and system resources. Configurable global
busing allows combining all of the device resources into a
complete custom system. The PSoC CY8C23x33 family can
have up to three I/O ports that connect to the global digital and
analog interconnects, providing access to four digital blocks and
four analog blocks.
DIGITAL SYSTEM
DigitalPSoCBlockArray
8
Row 0
4
4
8
8
8
DBB00
DBB01
DCB02
DCB03
PSoC Core
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
general Purpose I/O (GPIO)
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four million instructions per second MIPS 8-bit
Harvard-architecture microprocessor. The CPU uses an
interrupt controller with 11 vectors, to simplify programming of
real time embedded events. program execution is timed and
protected using the included sleep and watch dog timers (WDT).
Digital peripheral configurations are:
■ PWMs (8-and 16-bit)
Memory encompasses 8 KB of flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the flash. Program flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
■ PWMs with Dead band (8- and 16-bit)
■ Counters (8- to 32- bit)
■ Timers (8- to 32- bit)
■ UART 8 bit with selectable parity (up to 1)
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz internal main oscillator (IMO) accurate to
±2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz internal low speed oscillator (ILO) is provided for the
sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
■ Serial peripheral interface (SPI) master and slave (up to 1)
■ I2C slave and multi master (1 available as a system resource)
■ Cyclical redundancy checker (CRC)/Generator (8 to 32 bit)
■ IrDA (up to 1)
real time clock (RTC) and can optionally generate
a
■ Pseudo Random Sequence Generators (8- to 32- bit)
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a system
resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in the table titled PSoC Device Character-
istics on page 5.
Document Number: 001-44369 Rev. *G
Page 3 of 53
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