CY8C24123A
CY8C24223A
CY8C24423A
PSoC® Programmable System-on-Chip
PSoC® Programmable System-on-Chip
■ New CY8C24x23A PSoC device
❐ Derived from the CY8C24x23 device
❐ Low power and low voltage (2.4 V)
Features
■ Powerful Harvard-architecture processor
❐ M8C processor speeds up to 24 MHz
❐ 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Operating voltage: 2.4 V to 5.25 V
❐ Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
■ Additional system resources
❐ I2C slave, master, and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection (LVD)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
❐ Industrial temperature range: –40 °C to +85 °C
■ Advanced peripherals (PSoC® blocks)
❐ Six rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
■ Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured, in-circuit emulator (ICE), and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
Logic Block Diagram
Analog
Port 2 Port 1 Port 0
Drivers
PSoC CORE
• Full-duplex universal asynchronous receiver transmitter
(UART)
System Bus
• Multiple serial peripheral interface (SPI) masters or slaves
• Can connect to all general-purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
Global Digital Interconnect
Global Analog Interconnect
SRAM
256 Bytes
SROM
Flash 4KB
■ Precision, programmable clocking
❐ Internal ±2.5% 24- / 48-MHz main oscillator
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
❐ High accuracy 24 MHz with optional 32 kHz crystal and
phase-locked loop (PLL)
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
❐ Optional external oscillator up to 24 MHz
❐ Internal oscillator for watchdog and sleep
DIGITAL SYSTEM
ANALOG SYSTEM
■ Flexible on-chip memory
Analog
Ref
❐ 4 KB flash program storage 50,000 erase/write cycles
❐ 256-bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
Digital
Block
Array
Analog
Block
Array
Analog
Input
Muxing
❐ Flexible protection modes
❐ Electronically erasable programmable read only memory
(EEPROM) emulation in flash
■ Programmable pin configurations
❐ 25-mA sink, 10-mA source on all GPIOs
Internal
Voltage
Ref.
Switch
Mode
Pump
Digital
Clocks Accum.
Multiply
POR and LVD
System Resets
I2C
Decimator
❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
SYSTEM RESOURCES
❐ Eight standard analog inputs on all GPIOs, and
four additional analog inputs with restricted routing
❐ Two 30 mA analog outputs on all GPIOs
❐ Configurable interrupt on all GPIOs
Cypress Semiconductor Corporation
Document Number: 38-12028 Rev. *R
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 24, 2012
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数据手册
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